Further update on Hw implementations of AES-OTR

[Kazuhiko Minematsu]

Dear all,

Please find the attached hardware implementations of AES-OTR.
This is a further update from the previous one which includes single/dual/quad-core
architechtures with improved Throughput/area.
For a parameter called OTRC, an experimental, unoptimized Hexa-core version
is also included.
These implementations follow the latest specification, v3.5, which I submitted
to this mailing list on June 5th.

For reference, our synthesis results on Stratix V with default complier options
are also attached.

Best regards,
Kazuhiko Minematsu on behalf of the implementation team (
Naofumi Homma, Rei Ueno, Tomonori Iida, Eita Kobayashi and myself).