Hardware Development Package & Implementer's Guide v2.0

[Kris Gaj]

Dear All,

It is our pleasure to announce the new

 1) Development Package for Hardware Implementations Compliant with the CAESAR Hardware API, and

 2) Implementer’s Guide to Hardware Implementations Compliant with the CAESAR Hardware API,

both released as versions 2.0.

The main new features include:

 - full support for the development of lightweight implementations, 

   optimized for minimum area, power, and energy per bit,

 - extended support for the development of high-speed implementations,

   covering all Round 2 and Round 3 CAESAR candidates, except Keyak,

   optimized for maximum throughput/area and throughput,

 - improved support for experimental testing using FPGA boards, in applications

   with intermittent availability of input sources and output destinations.

   

The full set of new features is described at

   https://cryptography.gmu.edu/athena/CAESAR_HW_API/history.html 

  

The one-stop download page is available at

   https://cryptography.gmu.edu/athena/index.php?id=CAESAR   

See

1) Development Package

   under 

   CAESAR Hardware API v1.0

   Code

   

2) Implementer's Guide 

   under 

   CAESAR Hardware API v1.0

   Documentation

   Direct link: 

      https://cryptography.gmu.edu/athena/CAESAR_HW_API/CAESAR_HW_Implementers_Guide_v2.0.pdf

      

We recommend switching to the new version of the Package,

and the associated Implementer's Guide, for any future hardware 

development efforts, especially those related to the evaluation of

a) Use Case 1 CAESAR Candidates

b) Authenticated cipher cores intended to be experimentally tested, e.g., for the purpose 

   of evaluating side-channel resistance, power & energy measurements, 

   or to be used as a part of a bigger hardware system

c) Round 4 CAESAR candidates and/or the Final Portfolio.

The migration from the previously used Development Package v1.0 to 

the newly adopted Development Package v2.0 is relatively straightforward, and 

explained in the respective sections of the Implementer's Guide.

      

We would like to acknowledge 

 - all CAESAR candidates submitters, and

 - all hardware development teams

for providing us with the strong motivation and useful feedback for this project.

We would like to express special gratitude to our colleagues from 

Technische Universität München (TUM), Germany - Michael Tempelmeier and Fabrizio De Santis - 

for reporting and proposing solutions to multiple problems related to the practical experimental testing of CAESAR 

candidate cores and for validating several example cores developed using 

our new Development Package.

We hope that the release of this Package and related Guide will further 

 - simplify and speed-up any future hardware development efforts,

 - make the developed cores easier to integrate into real-world systems, and

 - accelerate the remaining phases of the CAESAR candidate evaluation.

 

Any comments, questions, and suggestions for the modifications & extensions are very welcome!

 

Good luck with all your new and upgraded designs!

GMU Benchmarking Team

https://cryptography.gmu.edu/athena 

https://cryptography.gmu.edu