WDI to IDE adaptor (4)

[Mike Arnold]

Aron, I had a (final) thought relating to testing the board. I have not specified any test points because my prototype is DIP therefore I just hang a probe off a chip leg. I cannot do that in SMD-land. Although I have identified many potential test points, there are only 7 where I think we need a distinct pad. All the others can be accessed by DIP chip legs. If it is possible to put in 7 pads (as below) that should be really helpful.

TP1 U22-5 2s timer output

TP2 U23-1 50ns W60h pulse

TP3 U45-6 50ns R60h pulse

TP4 U28-6 50ns delayed W60h pulse

TP5 U40-8 50ns burst clock trigger

TP6 U27-2 50ns primer clock trigger

TP7 U26-2 22.579MHz clock.

If I get time over my holidays I will continue work on the board test schedule along with the software (EEPROM based).

Thanks for all your support in this.

Mike

[Mike Arnold]

To give an idea of the test ROM software that I will be writing in due course, I have drafted some user instructions. I am open to suggestions and improvements. Note that I have not done any coding for this yet. The idea is to be able to identify faults on the board so that it can be repaired.
Mike

[Mike Arnold]

An update... 

After a bit of a break, Aron and I are back on the case.

I am part way through building a second (hand wired) prototype because the first prototype is now my day-to-day hard disk. Also, I am wiring the second one from the Kicad drawings as another verification of the circuit. When that is done, I will write the diagnostics and Aron will be in a position to finish the layout.

[Mike Arnold]

Well, I have got the second hand-wired prototype booting Cromix so its initial test is promising. This was wired from the Kicad circuits. More testing to come and then to write the test software.

Because I have a few different components in my shed this circuit is slightly different to the Kicad version (eg incorporates +5V to -5V inverter, uses original oscillator design, DIP RAM chip, original circuit around MAX232) but no major deviations really.

Aron, the only error I found was that U103-11 needs to be tied to +5V. Hats off to you for transcribing a big circuit so faithfully.

For those that are interested, it took me 50 man-hours to wire and debug the second prototype. 

Mike

[Aron Hoekstra]

Wow, looks awesome! I'd love to see the underside of that board! I have never had the desire to learn wirewrapping, but seeing how many chips you can squeeze on the top side with this approach, I can see the appeal.

Glad the schematic was mostly accurate! Wow yeah U103-11 wasn't connected to anything at all, not sure how that was missed - that is now updated.

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[Mike Arnold]

I didn't use wire wrap because it becomes difficult in high density layouts and the IC sockets and pins are very expensive. I soldered it all using 0.19mm enamelled wire and plenty of patience! I estimate around 900 solder joints and lots of cups of tea to keep me going. This has taught me that a PCB is definitely the way to go!

I attach a picture of the knitting on the underside as requested. I also include a picture of what happened to prototype 1 in case you wondered.

[Aron Hoekstra]

Oh my god, as expected: this underside gives me anxiety just looking at it! Amazing work though, and I really like how that enclosure turned out.

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