As a reminder, the next Corundum developer meeting will be taking place
as scheduled on Wednesday September 4, 2024 at 9:00 AM pacific time
(16:00 UTC).
Now that SIGCOMM is behind us (where we presented the Realizing RotorNet
paper) and the research project at UCSD has more or less wound down,
it's a good opportunity to discuss how to make Corundum a sustainable
project in the long term. Please tune in to the discussion if you can,
but I am certainly open to offline discussions as well.
Summary: Corundum is a large and complex project that likely will
require several people working full-time for continued maintenance and
development in the long term. I think that the best way to make this
work is for the project to be self-sustaining, and unfortunately I don't
think that is going to be possible with the current permissive license.
Therefore, I am planning a rewrite of the works (corundum and all of the
verilog libraries) in System Verilog under the CERN OHL strict license
(similar to GPL) + a CLA, with an option for a paid commercial license.
A rewrite also provides the opportunity to make deeper architectural
changes, including supporting higher link rates including potentially
400G, higher PCIe rates including potentially gen 5 x16, improved
descriptor format and descriptor handling, descriptor inline data,
improved driver interface, improved time synchronization capabilities
including white rabbit and PTM, SR-IOV, RDMA, XDP, possibly VFIO, and
much more.
Calendar:
https://calendar.google.com/calendar/embed?src=6784b9ed971221ccfe78513753b3743d24db63ef75a657bdddade1f5e2fd9d2c%40group.calendar.google.com
Meeting information:
https://github.com/corundum/corundum/wiki/Corundum-Developer-Meeting
Zoom link:
https://ucsd.zoom.us/j/94871106964?pwd=dHg2UGU3WDBXOHU0NEdITkVYdGVSUT09
Meeting ID: 948 7110 6964
Password: rdma
--
Alex Forencich