Transistor Data

[Mohammed Faerber]

Thedatasheet gives the gain for Ic=5mA and Vce=2V as 25, and the remainder of the results seem to indicate something of a bell-curve of the gain plotted against Ic, which with some rough interpolation would allow you to find a very rough and approximate gain for any Ic value in between 5mA and 500mA; although this is all for a Vce=2.

The graph gives a shape expected of the results, but the tabular results don't seem to match the graph (i.e. 150 mA should be 40, but graph value seems closer to 160 - i.e. the maximum). It seems the graph is plotting the maximum gain rather than minimum - doesn't make the graph useless?

The tabular data, while useful is strictly for the stated values of Ic=50-500mA and Vce=2. Obviously, 2V is quite low, so if this was part of a circuit running at Vce=5 and the Ic pulling say 100mA, then how could this datasheet ever be useful, considering those values can't even be found in the datasheet?

As they've not labelled the different curves it looks pretty dubious to me. Normally the graph would apply to typical values so you would not necessarily find them in the tabulated values (this one does not show typical values).

I might guess it's showing you either temperature (highest trace would be highest temperature, lowest trace lowest temperature) or unit to unit distribution for the high gain version, with the middle trace the typical value. For what it's worth, the graph is unchanged from the Motorola BC635 datasheet. In any case, the relevant curve is probably the middle one.

hFE is not very dependent on Vce once Vce is high enough, so typically the gain would be around 150 at 100mA and 5V, but it might be as low as a bit less than 40 or as high as a bit more than 160 (assuming 25C, and assuming it could be any of those transistor types.

So you should design your circuit so it will function for hFE between (say) 35 and 180 and you'll be fine. If you need higher gain, or tighter beta specifications, other transistors have higher gain at 100mA and in some cases you can specify the beta bin to reduce the range to more like 2:1 than 4:1 (best avoided if you can).

Edit: To clarify where the numbers came from- what I get from the graph (taking the middle curve) is that the gain does not typically change much between 150mA and 100mA, so we can reasonably assume similar limits. Those limits (not the graph) are what is guaranteed for the transistor. Only those. It's dropping pretty fast above 150mA so I would not make the same assumption if you said 200mA. The 40 and 160 (from the tables) are hard guarantees of transistor performance (you can complain to the supplier if the transistor does not perform within those limits). The curves illustrate what usually happens under some conditions and if the transistor does something different, you have no cause to object.

Gain vs. Vce, as you get much above saturation (when Vce >> Vbe, say above a volt or so) the gain hardly changes. 2V is well above 1V, as is 5V, so we can expect the gain to be almost the same. To illustrate this, consider this set of 2N3904 curves:

If the gain stayed constant the lines would be horizontal with voltage- they are not quite horizontal at higher base currents, but they are reasonably horizontal, and (more importantly in your example) the gain is only higher at higher Vce, so we're fine on the low end, but had better add a bit to the maximum gain guarantee.

Sometimes you must just give up on a transistor if you can't trust the data sheet. For instance, there are three curves in the graph and they are unknown i.e. On-Semi have failed to give relevant information about what those curves mean or represent.

Unless there is something great about the transistor that is embodied elsewhere in this data sheet I'd give up and find a BJT with a data sheet I could trust. If you need it resolved because you have (say) just bought a kilo of these parts then start digging around other manufacturer's of this device to see what their data sheets say.

β (beta), the gain or amplification factor of a transistor, normally is given when solving a circuit equation. However, if it is not given, it can be calculated if the currents, Ib (the base current) and either Ie ( the emitter current) or Ic (the collector current) are known.

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A field-effect transistor, which is the key element of modern complementary metal oxide semiconductor (CMOS) technology, is used in microprocessors, static random access memory and other digital logic circuits. Nevertheless, the future of CMOS is not clear, since both the miniaturization of single-element sizes and the operational speed will reach their ultimate limits in the near future1. Therefore, one of the primary tasks facing modern science is the search for alternative concepts to CMOS. Distinct achievements in this direction are the development of transistors based on carbon nanotubes and graphene nanoribbons2,3, spin torque transistors4,5 as well as three-dimensional spintronic circuits6. However, these approaches do not resolve another drawback of CMOS technology: the generation of waste heat during switching that is responsible for an increase in the power consumption of CMOS devices. Moreover, the waste heat increases with increasing data-processing speed due to the high switching frequencies. This fundamental drawback is inherent not only in CMOS, but in electronics in general since it is associated with a translational motion of electrons. Thus, there is a strong need for the development of new particle-less technologies for data transport and processing. Magnons, which are the quanta of spin waves7,8, are excellent candidates for carriers in such technologies.

Magnonics, the field of science dealing with magnon-based data operations9,10,11,12, encompasses a full spectrum of phenomena used in general wave-based signal processing13,14,15,16,17. The data can be coded into magnon phase or density and processed using wave effects such as interference. This approach has already been realized in spin-wave logic gates performing XNOR and NAND operations18,19,20,21. The main drawback of these gates is that the input data were coded in a form of direct current electric pulses manipulating magnon phases, while the output signal was carried by the magnons themselves. Obviously, that made it impossible to combine two logic gates without additional magnon-to-voltage converters. Moreover, the processing of large amounts of data has to be made on the same magnetic chip exclusively within the magnonic system. This fact stimulated a search for a way to control one magnon by another magnon and for the development of the all-magnon device presented in this paper. In addition, recent discoveries in the fields of spin transfer torque22,23, spin pumping and inverse spin Hall effects24,25,26 made it possible to perform interconversion of currents of magnons to electron-carried spin- and charge-currents and combine, in such a way, magnonic circuits with spintronic or CMOS devices.

Here we report on the realization of an insulator-based magnon transistor. The information is carried and processed in this three-terminal device using magnons and is fully decoupled from free electrons. The device demonstrated here has the potential to be scaled down27 to the sub-ten nanometer scale using exchange magnons26,28. Regarding frequency, there is large potential for ultra-fast data processing since magnon frequencies can reach up into the THz range28,29,30.

The four-magnon scattering process is not the only mechanism that might take place in the magnon transistor. With further increase of the magnon density, the YIG saturation magnetization decreases resulting in a shift of the dispersion relation and the magnon spectrum towards lower frequencies37. To prove the absence of this mechanism in our experiments, we have measured the magnon transmission spectrum in the presence of G-magnons, see Fig. 3c, where the first band gap and the two neighbouring transmission bands are shown. One can see that a suppression of the magnon transmission, rather than a shift of the band gap as shown in ref. 37, takes place. This proves that the four-magnon scattering mechanism occurring in the transistor is more efficient and requires smaller magnon densities. Additionally, Fig. 3c shows that no heating effects influence our experiments since these would result in a shift of the band gap45. From an applications point of view, the equivalent suppression of the source-to-drain magnon current in the transmission bands independently from the magnon frequency allows for the transistor to operate simultaneously with several source signals separated in frequency.

The main idea of the manuscript is to show that all-magnon data processing is possible solely within a magnonic system. To demonstrate this experimentally, the proof of concept magnon transistor was developed. Nevertheless, in the final part of the manuscript, we would like to discuss the potential of the magnon transistor from the point of view of practical application. The most crucial questions such as device sizes, operational frequencies and energy consumption are discussed below.

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