Release v15.03.8: a driver update for tiled fpgas

[Jamey Hicks]

We are working on support for multiple independent FPGA applications via tiles and partial reconfiguration.

Release v15.03.8 requires a driver update but makes no change to the programming model. Connectal packages are available for Ubuntu, CentOS, and Debian and pre-built zynq runtime files are available at https://github.com/cambridgehackers/zynq-boot/

For those of you who are curious, a Tile in the shared environment looks much like Top in the current environment:

interface Tile#(type ext_type, numeric type numReadClients, numeric type numWriteClients);

   interface PhysMemSlave#(18,32) portals;

   interface ReadOnly#(Bool) interrupt;

   interface Vector#(numReadClients,MemReadClient#(DataBusWidth)) readers;

   interface Vector#(numWriteClients,MemWriteClient#(DataBusWidth)) writers;

   interface ext_type ext;

endinterface

Each tile would be loaded via partial reconfiguration into a Platform supporting one or more tiles:

interface Platform#(type pins, numeric type numMasters);

   interface PhysMemSlave#(32,32) slave;

   interface Vector#(numMasters,PhysMemMaster#(PhysAddrWidth, DataBusWidth)) masters;

   interface Vector#(16,ReadOnly#(Bool)) interrupt;

   interface pins pins;

endinterface

This is a work in progress, but there are a couple of tests in tests/test_tileread and tests/test_tilewrite.

Cheers,

Jamey