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regression test for relaxed memory order/missing barrier?
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Michael Haberler
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Jul 29, 2015, 12:21:11 PM
7/29/15
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to Concurrency Kit, Charles Steinkuehler, Mick Grant
hi,
I'd appreciate hints for a regression test which can reliably trigger on missing barriers, in particular on multicore ARM processors
maybe something like the Dekker's algorithm cited on page 78 ? :
http://www.engbloms.se/presentations/engblom-esc2007-slides-as-shown.pdf
thanks in advance,
- Michael
background: we're porting an multithreaded application from x86 to ARM multicores, and need to plug memory ordering issues without killing performance
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