Hello Guys,
One last piece of material for your 4th of July weekend: this was
one of the best sessions I attended at the USENIX 08 Technical
Conference:
Design Tradeoffs for SSD Performance
http://www.usenix.org/events/usenix08/tech/agrawal.html
my unedited on the fly (and likely to contain mistakes!) notes are
attached.
Best -F
----------
Morning/3
Nitin Argawal at al, UW Madison and MSFT research - Tradeoffs of SSD
Performance
plusses:
read performance
no spin-up/down cost
good power consumption
What's the problem?
NAND flash requires erasure before write
A rewrite requires a different location on disk!
-> different write behavior; erase slow operation, actual in-place
rewrite would cost speed
Limited serial bandwidth
Limited lifespan (number of write cycles)
Tradeoffs in all design aspects!
Page smallest unit of R/W
Block smallest unit of erasure
Pages grouped in blocks for erasure efficiency
- invalidate old mapping
- copy old block, with changes, to new location
Good sequential R/W, excellent random read
Poor random write
SSDs typically over-provisioned w/ spare capacity to reduce clearing
load
Serial Bottleneck - 8 Bit Bus
to improve, striping or interleaving at all levels can be used
Finite number of erasure cycles
Greedy cycling improves poor write leveling
maintain block high-low counts
maintain lists o hot/cold data for swapping (5% added latency when
this active)
Migration strategies are beneficial in proportion to th hot/cold data
ratio: if your hot data set is small, the migration strategy will
needlessly increase wear by migrating cold data that would never be
overwritten otherwise.
Composite strategies and numbers in the paper.