Xeon Phi Coprocessor Optimization

[Federico Lucifredi]

Hello Computing Performance,

  I am reading the MK book "Intel Xeon Phi Coprocessor High Performance Programming", and I just realized Intel has two whitepapers on Xeon Phi tuning already up on their site:

 http://software.intel.com/en-us/articles/optimization-and-performance-tuning-for-intel-xeon-phi-coprocessors-part-1-optimization#

 http://software.intel.com/en-us/articles/optimization-and-performance-tuning-for-intel-xeon-phi-coprocessors-part-2-understanding#

  The MIC architecture is interesting mostly because optimizing for a 10-core Xeon or a 100-core coprocessor works along the same lines, and tuning performed to increase parallelism for the coprocessor will benefit execution on a standard Xeon CPU as well -- given how time-expensive code optimization is, this is highly interesting.

 Best -F

 _________________________________________ 
 -- "'Problem' is a bleak word for challenge" - Richard Fish 
 (Federico L. Lucifredi) - flucifredi at acm.org - GnuPG 0x4A73884C 

[Federico Lucifredi]

Hello Computing Performance,

  I am revisiting the PHI, as Intel has killed the product line and eBay is awash in cheap hardware. Anyone here had experience using multiple PHI boards on a single server? I expect limited compatibility, so I am looking for speciic server models for such configurations. 

Best -F

[Kurt L Keville]

I know somebody who knows somebody... a guy who worked on the massive PHI cluster down at TACC.  I will ask him.​

---

From: computing-...@googlegroups.com <computing-...@googlegroups.com> on behalf of Federico Lucifredi <fluci...@acm.org>
Sent: Thursday, September 17, 2020 3:59 PM
To: Computing Performance
Subject: [computing-perf] Re: Xeon Phi Coprocessor Optimization

 

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