The Last Psion - Adding Modern Flash Storage and Wi-Fi to the Series 3c

64 views
Skip to first unread message

palt...@gmail.com

unread,
Sep 17, 2018, 4:48:40 PM9/17/18
to
To those Psion fans still clinging on to their SSDs!

This is the insane challenge I've decided to take on. I don't know if I'll end up finishing it, but I'm going to at least try.

https://hackaday.io/project/161291-the-last-psion

I want to build a device that will add modern storage and Wi-Fi to my ageing but beloved Psion Series 3c. If possible, I want it to fit into the SSD slot of the 3c and power it straight from the 3c.

If anyone has any access to unusual or rare software, documentation or photos for the Series 3c (or 3a and 3mx, for that matter), please let me know. I'm especially looking for newer versions of the SIBO HDK that also cover the 3c and 3mx.

Theo

unread,
Sep 17, 2018, 5:36:28 PM9/17/18
to
palt...@gmail.com wrote:
> To those Psion fans still clinging on to their SSDs!
>
> This is the insane challenge I've decided to take on. I don't know if I'll
> end up finishing it, but I'm going to at least try.
>
> https://hackaday.io/project/161291-the-last-psion
>
> I want to build a device that will add modern storage and Wi-Fi to my
> ageing but beloved Psion Series 3c. If possible, I want it to fit into
> the SSD slot of the 3c and power it straight from the 3c.

Sounds like fun.

The protocol is rather interesting. I think doing it in a CPLD (basic FPGA)
would probably be most flexible, but I can understand that's a place you don't
want to go. Also, you need to a device with 5V capability, which is quite
rare nowadays.

It sounds like the tricky bit is dealing with the up-to-5MHz input signal.
I wonder whether you could take a couple of 12-bit shift registers. One is
an input, which latches data coming out of the ASIC. The other is an
output, which you enable to send data to the ASIC. With a little bit of
control logic to handle synchronisation and latching, it essentially reduces
your 5MHz one-bit problem to a 400kHz parallel-word problem, which is a lot
easier to deal with in software.

Depending what you feel comfortable with, you could have a couple of shift
register chips in TTL logic, and then wrap up the control logic in another
programmable logic device (PAL, GAL, CPLD, whatever you prefer). Or maybe
it's simple enough to do in a few TTL logic gates.

Do you have oscilloscope traces[1]? That's where I'd start. (I wonder if
there's a way to work out which end is driving at any given time? For
instance, gimp the power supply so the SSD voltage is slightly lower than
the other, or something like that?)

Then try and write some logic to handle them and run it against the traces
in a simulator. Only when you're happy start building things. ('Simulator'
could be a pre-existing logic simulator, or something written in whatever
language you feel comfortable with)

Good luck!
Theo


[1] If you don't have anything suitable, I recommend this software:
https://sigrok.org/
using a cheap CY7C68013A logic analyser module (many sellers):
https://www.ebay.co.uk/itm/CY7C68013A-56-EZ-USB-FX2LP-USB2-0-Develope-Board-Module-Logic-Analyzer-EEPROM-A/253077661586

palt...@gmail.com

unread,
Sep 18, 2018, 6:17:44 PM9/18/18
to
On Monday, 17 September 2018 22:36:28 UTC+1, Theo wrote:
> Sounds like fun.
Fingers crossed!

> The protocol is rather interesting. I think doing it in a CPLD (basic FPGA)
> would probably be most flexible, but I can understand that's a place you don't
> want to go. Also, you need to a device with 5V capability, which is quite
> rare nowadays.
I hadn't heard of CPLDs before, although to be fair I didn't know much about FPGAs until a couple of days ago. I'll do some research into CPLD test boards. Even if I don't use it for this project, it'll be good to learn.

> It sounds like the tricky bit is dealing with the up-to-5MHz input signal.
> I wonder whether you could take a couple of 12-bit shift registers. One is
> an input, which latches data coming out of the ASIC. The other is an
> output, which you enable to send data to the ASIC. With a little bit of
> control logic to handle synchronisation and latching, it essentially reduces
> your 5MHz one-bit problem to a 400kHz parallel-word problem, which is a lot
> easier to deal with in software.
>
> Depending what you feel comfortable with, you could have a couple of shift
> register chips in TTL logic, and then wrap up the control logic in another
> programmable logic device (PAL, GAL, CPLD, whatever you prefer). Or maybe
> it's simple enough to do in a few TTL logic gates.
Converting to parallel with shift registers is a really good idea. How would that work with the data heading back to the Psion? Would I need to keep an eye on the first three bits from the Psion for a data request command, then get the output shift register to send data back?

> Do you have oscilloscope traces[1]? That's where I'd start. (I wonder if
> there's a way to work out which end is driving at any given time? For
> instance, gimp the power supply so the SSD voltage is slightly lower than
> the other, or something like that?)
I haven't got an oscilloscope, but I've just bought the logic analyser you linked to. Very pleased that Sigrok is open source and runs on Linux. The only examples of the protocol I have are from the HDK.[1] I'm going to make an adapter so that I can use an SSD from outside the Psion. That would make it easier for me to use a separate power source for the SSD, too. Alternatively, could I put something in the middle that would monitor the signals and separate them? Thinking about it, maybe a CPLD would do the trick...

> Then try and write some logic to handle them and run it against the traces
> in a simulator. Only when you're happy start building things. ('Simulator'
> could be a pre-existing logic simulator, or something written in whatever
> language you feel comfortable with)
>
> Good luck!
Thanks - looks like I'm going to need it!

[1] For reference, here is a link to the Psion SIBO Hardware Development Kit v1.00. I'm hoping that someone somewhere has a newer version covering the Series 3c and 3mx.
http://www.scss.com.au/family/andrew/pdas/psion/hdk.pdf

Theo

unread,
Sep 19, 2018, 6:24:24 AM9/19/18
to
palt...@gmail.com wrote:
> On Monday, 17 September 2018 22:36:28 UTC+1, Theo wrote:
> > Sounds like fun.
> Fingers crossed!
>
> > The protocol is rather interesting. I think doing it in a CPLD (basic
> > FPGA) would probably be most flexible, but I can understand that's a
> > place you don't want to go. Also, you need to a device with 5V
> > capability, which is quite rare nowadays.

> I hadn't heard of CPLDs before, although to be fair I didn't know much
> about FPGAs until a couple of days ago. I'll do some research into CPLD
> test boards. Even if I don't use it for this project, it'll be good to
> learn.

I've used the Altera MAX-II and some from Lattice (a long time ago). The
Altera ones use their FPGA tools, which are a bit unwieldy but OK when you
get into them.

I'd start with a chip that does 5V, and a dev board that has some example
projects you can modify. You don't need to know a whole lot of Verilog or
VHDL to write basic logic. It's better if you can run your code in a
simulator first, because then you can more easily see what's going on than
trying to probe hardware.

> Converting to parallel with shift registers is a really good idea. How
> would that work with the data heading back to the Psion? Would I need to
> keep an eye on the first three bits from the Psion for a data request
> command, then get the output shift register to send data back?

Something like that. You could clock the input and output shift registers
at the same time and then select one based on the direction. Or you could
have 8 bit in/out shift registers and then implement the remaining 4 bits in
discrete logic.

> > Do you have oscilloscope traces[1]? That's where I'd start. (I wonder if
> > there's a way to work out which end is driving at any given time? For
> > instance, gimp the power supply so the SSD voltage is slightly lower than
> > the other, or something like that?)

> I haven't got an oscilloscope, but I've just bought the logic analyser you
> linked to. Very pleased that Sigrok is open source and runs on Linux.
> The only examples of the protocol I have are from the HDK.[1] I'm going to
> make an adapter so that I can use an SSD from outside the Psion. That
> would make it easier for me to use a separate power source for the SSD,
> too. Alternatively, could I put something in the middle that would
> monitor the signals and separate them? Thinking about it, maybe a CPLD
> would do the trick...

One useful thing about CPLDs is you can largely decouple the physical/board
design from the logic. You can put down the CPLD on the PCB and then figure
out what logic you need later - as long as it still fits within the CPLD.
They are also handy for voltage conversion - for example, if you wanted to
attach to a Raspberry Pi or similar which has 3.3V I/O - you just wire up
I/Os of different voltages to different I/O banks on the CPLD, and set the
IOVCC of each bank to the voltage you need.

So a little breakout board with a CPLD, a connector for an ESP8266 (or
whatever you want), and some header pins for probing or taking to a
computer, might be a very useful first step.

Hmm, now I look it seems 5V capable CPLDs are getting rare now.
It might be worth trying an Altera MAX II board with an EPM240 part:

https://www.openimpulse.com/blog/products-page/product-category/max-ii-epm240-cpld-minimal-development-board/
https://www.ebay.co.uk/itm/1PCS-Altera-MAX-II-EPM240-CPLD-development-board-learning-board-breadboard-NEW-C/191911917944

and then adding a clamp diode/resistor arrangement described in ch8:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max2/max2_mii5v1.pdf

While this board is cheap, there's not a whole lot of info available for it.
So you could also look at other MAX II boards with better
documentation/tutorials. There are also tutorials for larger FPGAs (the
tools/design flow is largely the same) but you'd need to do some translation
for your board.

> Thanks - looks like I'm going to need it!

:-)

Theo

Theo

unread,
Sep 19, 2018, 6:31:43 AM9/19/18
to
Oops, that one doesn't have the programmer with it. Try this:
https://www.ebay.co.uk/itm/Altera-FPGA-CPLD-programmer-USB-Blaster-compatible-LC-MAXII-EPM240-Dev-Board/192192492414
'USB Blaster+development board' option

- as usual, same thing available from lots of sellers including some in the
UK for faster delivery

Theo

kelvin....@gmail.com

unread,
Oct 5, 2018, 3:14:28 AM10/5/18
to
Just wanted to add this is an AMAZING idea :D As much as I want to like the Gemini it is just an Android device with a good keyboard. The Psion's were much more than just the physical side, they were also a great simple operating system with powerful (if somewhat cut down) applications. I used my 3A to write reports on.

My dream has always been to have a Psion5 with modern connectivity but the classic OS updated to take advantage of it. Just wish I had the knowledge to be able to create it, I am limited to Arduino's lol

Good luck with this and if you are able to get a working device at the end, and sell it ;), I will certainly look at adding it to my retro hardware collection :D

palt...@gmail.com

unread,
Oct 8, 2018, 5:43:58 AM10/8/18
to
Thanks, Kelvin! I've had to pause this project for a couple of weeks - work has taken over, and I'm still waiting for the logic analyser to arrive from Hong Kong - but I'll be back on it in November. In the meantime I've been reading up on all the things I need to learn, as well as watching a lot of reverse-engineering videos on YouTube.

I also have a 5mx at home that I'd quite like to do something with in the future. It won't read any of my CF cards, not even ones I used to use in my old Series 5. I'm hoping it's something simple like a capacitor needing replacement, but I've not done any work with surface-mount electronics before.

Must dash, much to learn! :-)

palt...@gmail.com

unread,
Oct 30, 2018, 11:15:34 AM10/30/18
to
Just to update anyone who's interested, I've started working on this again. I posted an update on Hackaday.io just over a week ago.

https://hackaday.io/project/161291-the-last-psion/log/154934-the-ssd-port-and-finally-some-logic-analysis

Last weekend I had a breakthrough with interpreting the signals between the SSD and my sacrificial 3a. I'm hoping to make a bit more progress during the week and should be posting an update this weekend.

Meanwhile, I'm on the hunt for information. I've been trying to get in touch with people who were at Psion back in the early 90s and were involved with the development of the Series 3 range. I'm hoping beyond hope that someone out there still has some notes or documentation, even an email thread with some discussion on the kit.

The information I need is out there somewhere. I'm a little worried that some of it is still hidden behind NDAs somewhere in the Psion archives at Motorola Solutions (who bought Psion back in 2012). But maybe someone will take pity on this nerd and let me have a sneak peek.

I'm also on the scrounge for any Psion kit from that era that people no longer want. I'll happily accept broken/dead kit, too. I want some things I can pull apart without worrying too much about breaking it.

That's the story so far. Thanks for reading.

Alex
Reply all
Reply to author
Forward
0 new messages