MPC750: how to flush L2 cache?
Andrew Klossner
of L2 cache.
How does one flush (not just invalidate) the L2 cache?
-=- Andrew Klossner (and...@teleport.com)
Richard Woodruff
>of L2 cache.
>
>How does one flush (not just invalidate) the L2 cache?
Manual shows it can be configured as write-thru L2CR[L2WT] :), it
also says it snoops, I would imagine that the need to flush would
depend on to what extent it snoops...
Richard W.
>
> -=- Andrew Klossner (and...@teleport.com)
Skipper Smith
>I'm looking at updating my 603e-based design with a 750 and a megabyte
>of L2 cache.
>
>How does one flush (not just invalidate) the L2 cache?
I don't have a routine written up for you, but it calls for creative use
of dcbz instructions being issued to an area of memory that you don't care
about. Setting the dcfa (data cache flush assist) bit in HID0 (or is in
in the L2 cache control register) will reduce the number of instructions
you need to execute in a loop. Someone else here may have the actual code
for you to use.
Good luck.
--
Skipper Smith Helpful Knowledge Consulting
Worldwide Microprocessor Architecture Training
PowerPC, ColdFire, 68K, CPU32 Hardware and Software
/* Remove no-spam. from the reply address to send mail directly */
David D. Smith
(Andrew Klossner) wrote:
> I'm looking at updating my 603e-based design with a 750 and a megabyte
> of L2 cache.
>
> How does one flush (not just invalidate) the L2 cache?
>
> -=- Andrew Klossner (and...@teleport.com)
On a Grackle: CF_FLUSH_L2.
d
T Greeniaus
> I'm looking at updating my 603e-based design with a 750 and a megabyte
> of L2 cache.
>
> How does one flush (not just invalidate) the L2 cache?
Disable interrupts. Disable relocation. Load a contiguous chunk of memory
of size (L2 + L1) (I usually use 2MB just to be safe). Then dcbf that same
are of memory and restore your MSR. If you disable the L1 cache first, you
can probably load just the size of L2 and then dcbf it all.
TG
Andrew Klossner
>> How does one flush (not just invalidate) the L2 cache [on a 750]?
Responding to several follow-ups:
> I don't have a routine written up for you, but it calls for creative use
> of dcbz instructions being issued to an area of memory that you don't care
> about. Setting the dcfa (data cache flush assist) bit in HID0 (or is in
> in the L2 cache control register) will reduce the number of instructions
> you need to execute in a loop.
DCFA in HID0 seems to be for the L1 cache. I don't find an equivalent
bit in the L2CR register. Do you mean that I have to DCBZ to my
entire megabyte of L2 cache?
> Manual shows it can be configured as write-thru L2CR[L2WT] :), it
> also says it snoops, I would imagine that the need to flush would
> depend on to what extent it snoops...
I need to configure as copy-back, and my circuit doesn't support
snoops. I don't even wire up the GBL line between the CPU and memory
controller. Snoop traffic causes significant degradation of
performance in my environment.
> On a Grackle: CF_FLUSH_L2.
I'm using the L2 support in the 750. I'm using a Chaparral, not a Grackle.
-=- Andrew Klossner (and...@teleport.com)
Skipper Smith
>I wrote:
>
>>> How does one flush (not just invalidate) the L2 cache [on a 750]?
>
>Responding to several follow-ups:
>> I don't have a routine written up for you, but it calls for creative use
>> of dcbz instructions being issued to an area of memory that you don't care
>> about. Setting the dcfa (data cache flush assist) bit in HID0 (or is in
>> in the L2 cache control register) will reduce the number of instructions
>> you need to execute in a loop.
>
>DCFA in HID0 seems to be for the L1 cache. I don't find an equivalent
>bit in the L2CR register. Do you mean that I have to DCBZ to my
>entire megabyte of L2 cache?
D'oh! Brain fart. Please excuse me. Yes, dcfa is for the L1 only. If
you don't know exactly what data is in the L2, then, yes, dcbz to the
entire 1 MB will definately do the trick. If you know the data, then just
dcbf to the areas that you know are in the L2 or L1 (I am assuming this
isn't the case, as it is hard to keep track). BTW, it was suggested that
the Minix kernal has the code to do this and it is freely available
[Thanks, Tim].
Welcome to the world of RISC (though it sounds like you have been here a
while). You get to do in software what others do in hardware, but now you
have the flexibility of doing anything else that might need to be done at
the same time (like service interrupts).
T Greeniaus
> D'oh! Brain fart. Please excuse me. Yes, dcfa is for the L1 only. If
> you don't know exactly what data is in the L2, then, yes, dcbz to the
> entire 1 MB will definately do the trick. If you know the data, then just
> dcbf to the areas that you know are in the L2 or L1 (I am assuming this
> isn't the case, as it is hard to keep track). BTW, it was suggested that
> the Minix kernal has the code to do this and it is freely available
> [Thanks, Tim].
You'll probably want to be careful if you go the dcbz route (especially if
this memory doesn't exist physically). That's probably the fastest way
(least amount of bus cycles) to flush the cache, but make sure you are
disabling interrupts first. You might want to configure the cache for
data-only first, in the unlikely event that you need to read in some code
during the flush operation. If you are dcbz'ing non-existant memory, either
dcbi it all at the end of the operation, or perform a global invalidate (not
sure what's faster, but I imagine a global invalidate would be).
TG
karthikey...@gmail.com
> I'm looking at updating my 603e-based design with a 750 and a megabyte
> of L2 cache.
>
>
> -=- Andrew Klossner (and...@teleport.com)
I'm also trying to achieve the flush functionality in e500mc processor, but not sure about the DCFA sequence. Would be good if you can share the details about the flush code with DCFA (if worked for you?).