IBM Power6 Processor architecture details from ISSCC

[Radeon]

IBM tips Power6 processor architecture

Mark LaPedus
EE Times
(02/06/2006 1:54 PM EST)

SAN FRACISCO - At the International Solid-State Circuits Conference
(ISSCC) here, IBM Corp. tipped its next-generation Power6 processor
architecture for servers.

In various papers at the event, IBM indicated that the Power6 is a
65-nm processor that operates in excess of 4-GHz. Built around
silicon-on-insulator (SOI) and other technologies, the Power6 is the
follow-on processor to the company's current Power5 architecture.

In one paper, the company described a 5.6-GHz Power6 processor with
64-Kb of Level 1 data cache. The processor is said to have an
eight-way, set-associative design with a two-stage pipeline supporting
two independent reads or one writes per cycle.

IBM also makes use of a 5-GHz duty-cycle correction clock distribution
network for the processor. In the network, the company implements a
copper distribution wire that is 3 microns wide and 1.2 microns thick.

In another paper, IBM described low-latency fixed-point and binary
floating-point units for the Power6. The floating-point unit
incorporates "many microarchitectures, logic, circuit, latch and
integration techniques to achieve [a] 6-cyle, 13-FO4 pipeline,"
according to the company's paper.

The Power6 design uses dual power supplies, a logic supply in the
0.9-to-1.2 Volt range and an SRAM power supply at about 150-mV higher.

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