Synthesis problem

[Sarah Salehzadeh Nobari]

I have been trying to synthesise a VHDL file and Auotlogic VHDL does not
synthesise the file as described below:

The VHDL file is used for defining an algorithm for calculating the
intersection point between two lines. The file makes use of an asynchronous
reset which has been defined in the following format :

ENTITY intersect_arch IS
PORT(rst : IN BIT ;
clk : IN BIT ;
latchenable : IN BIT ;
data_in : IN QSIM_STATE_VECTOR(47 DOWNTO 0) ;
data_out : OUT QSIM_STATE_RESOLVED_X_VECTOR(QSIM_STATE_VECTOR(47 DOWNTO 0)) BUS ;
outputready : OUT BIT :
. . . ) ;
END intersect_arch ;

ARCHITECTURE behave OF intersect_arch IS

BEGIN

algorithm : PROCESS
BEGIN
WAIT ON clk, rst ;
IF (rst = '1') THEN
outputready <= '0' ;
. . .
ELSIF (clk = '1' AND clk'LAST_VALUE = '0' AND clk'EVENT) THEN
. . .
IF (latchenable = '1') THEN
data_out <= data_in ;
outputready <= '1' ;
ELSE
data_out <= NULL ; -- Tri_state output
END IF :
END IF ;
END PROCESS algorithm ;
END behave ;

It must be pointed out that the above program is only part of the overall
program. When the VHDL file is synthesised, it comes up with the following
error message :

"Asynchronous reset and tri_states for process "algorithm" NOT supported"

When I remove the asynchronous reset, the synthesis is carried out but the
asynchronous reset obviously causes problems.

I have looked in the AUTOLOGIC VHDL reference manual and it mentions a
temporary signal but I am not sure how that works.

Any help would be appreciated

Thanks,
Sarah

[Rich Hatcher]

In article 7...@oak45.doc.ic.ac.uk, ss...@doc.ic.ac.uk (Sarah Salehzadeh Nobari) writes:
>I have been trying to synthesise a VHDL file and Auotlogic VHDL does not
>synthesise the file as described below:

[VHDL deleted]

>Any help would be appreciated

I rewrote your VHDL to the following (because of compile problems and
trying to find a solution) but get the same error in Autologic:

LIBRARY mgc_portable;
USE mgc_Portable.qsim_logic.ALL;

ENTITY inter_arch IS
PORT(rst : IN qsim_state ;
clk : IN qsim_state ;
latchenable : IN qsim_state ;
data_in : IN QSIM_STATE_RESOLVED_X_VECTOR(47 DOWNTO 0) ;
data_out : OUT QSIM_STATE_RESOLVED_X_VECTOR(47 DOWNTO 0) BUS ;
outputready : OUT qsim_state ) ;
END inter_arch ;

ARCHITECTURE behave OF inter_arch IS
SIGNAL data: QSIM_STATE_RESOLVED_X_VECTOR(47 DOWNTO 0);

BEGIN
algorithm : PROCESS
BEGIN
WAIT ON clk, rst ;

IF rst = '1' THEN
outputready <= '0' ;
ELSIF clk = '1' AND clk'LAST_VALUE = '0' AND clk'EVENT THEN
IF latchenable = '1' THEN

data_out <= data_in;
outputready <= '1';
ELSE
data_out <= NULL ;

outputready <= '0' ;

END IF ;
END IF ;
END PROCESS algorithm ;
END behave ;

I then separated the flip-flop function from the tristate function
into two processes and this worked:

LIBRARY mgc_portable;
USE mgc_Portable.qsim_logic.ALL;

ENTITY intersect_arch IS
PORT(rst : IN qsim_state ;
clk : IN qsim_state ;
latchenable : IN qsim_state ;
data_in : IN QSIM_STATE_RESOLVED_X_VECTOR(47 DOWNTO 0) ;
data_out : OUT QSIM_STATE_RESOLVED_X_VECTOR(47 DOWNTO 0) BUS ;
outputready : OUT qsim_state ) ;
END intersect_arch ;

ARCHITECTURE behave OF intersect_arch IS

SIGNAL data: QSIM_STATE_RESOLVED_X_VECTOR(47 DOWNTO 0);

BEGIN
algorithm : PROCESS
BEGIN
WAIT ON clk, rst ;

IF rst = '1' THEN
-- other reset functions
ELSIF clk = '1' AND clk'LAST_VALUE = '0' AND clk'EVENT THEN
data <= data_in ; -- flip-flop function

END IF ;
END PROCESS algorithm ;

tri_buf: PROCESS(rst, latchenable, data)
BEGIN
IF rst = '1' THEN
outputready <= '0' ;
ELSIF latchenable = '1' THEN
data_out <= data;

outputready <= '1';
ELSE
data_out <= NULL ;

outputready <= '0' ;
END IF ;
END PROCESS;
END behave ;

Autologic messages:

// Synthesizing VHDL
//
// Note: Synthesizing VHDL Design /home1/hatcher/mentor/autologic/code/intersect_arch, Entity intersect_arch, Architecture behave.
//
// <><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
// Processing started at Wed Jun 1 09:58:47 1994

//
// Clock / Finite State Machine Analysis
//
// [Line 16] The asynchronous reset signal for the process "algorithm" is "rst".
// [Line 16] The rising-edge-triggered clock for the process "algorithm" is "clk".
//
// Synthesizing Design
//
// Entity intersect_arch.behave
// Process algorithm
// Latching outputs.
// Using D flip-flop (default).
// Inserting flip-flops for:
// data
// Process tri_buf
// Inserting transparent latches for:
// data_out
// Inserting tri-states for:
// data_out
//
// High Level Optimization
//
// Component intersect_arch.behave
//
// Netlisting
//
//
// Sequential components instantiated:
// 48 D flip-flops.
// 48 D latches.
//

Since outputready can't be driven from two processes, I placed
it in the tri_buf process. If you want it to be a flip-flop
you need to place it in the algorithm process. But then you
could have a full clock difference between the output and the
outputready signal which seems like something to avoid. There
are probably several ways you could arrange things.

Hope this "work-around" helps.

[macy...@gmail.com]

salam sara jan, neshasteh boodam paie computer, iade roozhaie ghadimo kardam, esmeto too google search kardam va jalebeh keh in matn oomad. kheli jalebeh keh adam hama ro mittoneh too internet peida koneh, che tori? khoobi? agehmano iadeteh, too facebook searcham koni rahat peidam mikoni.

khoshhal misham azat bakhabar besham, ghorboonet Mehrzad Shahrokhzadeh az zaman haie gozashteh too Farasat