387 in AT-386

[Linus Benedict Torvalds]

Ok, I posted this on c.s.ibm.pc.hardware some time ago, but got no
answers. Maybe you can help:

>Hello netters,
>
>As I've gotten nice replies from you before, I'll try the net.wisdom
>once more. I've got this problem with a 387 on an AT-clone running in
>protected mode on this unix-clone of mine:
>
>It seems the 387 #ERROR-pin is wired through some electronics to the
>IRQ13 pin on the slave 8259A, and latching among others the PEREQ and
>BUSY pins on the 386. Correct?
>
>It also seems the #ERROR pin on the 386 is grounded. Tell me it isn't
>so, please...
>
>That's how far I've gotten with the meager docs I've got. The latching
>of the PEREQ/BUSY pins seem to be cleared by writing 0 to port 0xf0, but
>I'd be very interested to hear all the gory details:
>
>Can you activate the #ERROR pin on the 386 side by some magic
>incantation (write xx to port yy?), disconnecting the IRQ13/latching
>hardware if possible? What I'd want is the "normal" 386/387 binding,
>with #error pins just wired together. Is this at all possible on an
>AT(386)?
>
>What exactly does port 0xf0 do? Can you do anything other than just
>clear the latch? Bitpatterns anyone?
>
> Linus Torvalds (torv...@kruuna.helsinki.fi)
>
>PS. As always, I'm a poor student, and while pointers to nice books (for
>just $499.95, sigh) are wellcome, free advice is even more so.
>
>PPS. Just get a 486, and set/reset the right bit in cr0 isn't the
>answer either, as that costs even more than the books :-(
>
>PPPS. Notice how I don't have a 10-line .sig, but I still get to clutter
>up your screen with these never-ending post-scripts :-) Wow.

[Mark Robert Thorson]

You've described the floating-point error reporting mechanism fairly
accurately. For backwards compatibility with the original PC/XT,
all PC-compatible systems report errors by raising an interrupt line.
The I/O reference is needed to clear the latch which maintains the error.

This mechanism is different from the mechanism Intel introduced in
the 286/287 and continued in the 386/387. For compatibility with the
PC, the 486 has pins which allow the PC-style interface to be implemented.

On the AT, ERROR# to the 286 is tied high, and ERROR# from the 287
goes to INT13. The BUSY# output from the 287 is latched, and then drives
the BUSY# input to the 286. The INT13 service routine is expected to
do a write to I/O address 0F0 (hex) to clear the latch.

On the XT, the INT output of the 8087 is one of several possible sources
of NMI to the 8088. On the AT, the INT13 service routine clears the latch,
then jumps to the NMI service routine.

This mechanism benefits the end user because it allows him to keep
his investment in all that great PC/XT software :-)