Personal Computer CHIPLIST 9.9.5 part 1 of 5

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Archive-name: pc-hardware-faq/chiplist/part1
Last-modified: 1998/06/14
Version: 9.9.5


CHIPLIST 9.9.5 by Aad Offerman, 1998/07/26.


A. Offerman
Bonnweg 40
3137NE Vlaardingen
The Netherlands
+31-(0)10-4745386
+31-(0)6-54795060


Since there are a lot of questions about the differences between the various
chips used in the IBM PC, IBM PC/XT, IBM PC/AT, IBM PS/2 and compatibles, this
list, containing their CPUs and NPXs, has been compiled for the benefit of
the net community. I hope it can answer some questions.

This list is the result of collecting many snippets of information from
USENET News and data books. Furthermore, various contributors and others have
helped to make this list to what it is today. Thank you all.

Any corrections, additions, or comments are welcome. Please reply by E-mail
to:
offe...@einstein.et.tudelft.nl

This list is cross-posted about once every month to the following newsgroups:
comp.sys.ibm.pc.hardware.chips
comp.sys.ibm.pc.hardware.systems
comp.sys.ibm.pc.hardware.misc
comp.ibm.pc.hardware
comp.sys.ibm.pc.misc
comp.sys.intel
comp.answers
news.answers

The latest version of this list can also be obtained from:
rtfm.mit.edu /pub/usenet/news.answers/pc-hardware-faq/chiplist/
ftp.twi.tudelft.nl /pub/texts/chiplist/chiplist.asc

The WWW HTML version of the latest Chiplist is available at:
http://einstein.et.tudelft.nl/~offerman/chiplist.html

The complete Chiplist in a single WWW HTML document is available at:
http://einstein.et.tudelft.nl/~offerman/chiplist.long.html


Contents


1 Introduction
1.1 Identification
1.2 Packages
1.3 Semiconductor processes
1.4 JEDEC (Joint Electronic Device Engeneering Council)
1.5 Manufacturers
1.5.1 Intel
1.5.2 AMD (Advanced Micro Devices)
1.5.3 IBM (International Bussiness Machines)
1.5.4 Chips & Technologies
1.5.5 Cyrix
1.5.6 Texas Instruments
1.5.7 UMC
1.5.8 NexGen
1.5.9 IIT (Integrated Information Technology)
1.5.10 Motorola
1.5.11 Apple
1.5.12 HP
1.5.13 DEC (Digital Equipment Corporation)
1.5.14 Renaissance Microsystems Inc.
1.5.15 IDT (Integrated Device Technology)
1.6 References

2 CPU (Central Processing Unit)
2.1 Introduction
2.2 Intel i4004 CPU
2.3 Intel i4040 CPU
2.4 Intel i8008 CPU
2.5 Intel i8080/i8080A CPU
2.6 Zilog Z80 CPU
2.7 Intel i8085A/i8085AH CPU
2.8 Intel i8086A/i80C86A CPU, Intel i8088A/i80C88A CPU
2.8.1 Intel i8086A/i80C86A CPU
2.8.2 Intel i8088A/i80C88A CPU
2.9 AMD Am8086/Am80C86 CPU, AMD Am8088/Am80C88 CPU
2.9.1 AMD Am8086/Am80C86 CPU
2.9.2 AMD Am8088/Am80C88 CPU
2.10 Harris HS80C86/883 CPU, Harris HS80C88/883 CPU
2.10.1 Harris HS80C86/883 CPU
2.10.2 Harris HS80C88/883 CPU
2.11 Siemens SAB8086 CPU, Siemens SAB8088 CPU
2.11.1 Siemens SAB8086 CPU
2.11.2 Siemens SAB8088 CPU
2.12 Hitachi H80C88 CPU
2.13 Contemporary CPUs
2.14 Intel i80186/i80C186 CPU, Intel i80188/i80C188 CPU
2.14.1 Intel i80186/i80C186 CPU
2.14.2 Intel i80188/i80C188 CPU
2.15 AMD Am80186/Am80188 CPU
2.15.1 AMD Am80L186 CPU
2.15.2 AMD Am80L188 CPU
2.15.3 AMD Am186EM CPU
2.16 NEC V30/V20 CPU
2.16.1 NEC V30 CPU
2.16.2 NEC V20 CPU
2.17 Siemens SAB80186 CPU, Siemens SAB80188 CPU
2.17.1 Siemens SAB80186 CPU
2.17.2 Siemens SAB80188 CPU
2.18 Intel i80886 CPU
2.19 Intel i80286 CPU
2.20 AMD Am80286/Am80C286 CPU
2.21 Harris 80C286 CPU
2.22 Siemens SAB80286 CPU
2.23 Fujitsu 80286 CPU
2.24 Kruger 80286 CPU
2.25 Intel i80386 CPU
2.25.1 Intel i80386/i80386DX CPU
2.25.2 Intel i80386SX CPU
2.25.3 Intel i80386SL CPU
2.25.4 Intel RapidCAD CPU
2.25.5 Intel i80376 microprocessor
2.25.6 Intel i386SX microprocessor
2.25.7 Intel i386CX microprocessor
2.25.8 Intel i386EX microprocessor
2.26 AMD Am386 CPU
2.26.1 AMD Am386DX CPU
2.26.2 AMD Am386DXL CPU
2.26.3 AMD Am386DXLV CPU
2.26.4 AMD Am386SX CPU
2.26.5 AMD Am386SXL CPU
2.26.6 AMD Am386SXLV CPU
2.26.7 AMD Am386DE CPU
2.26.8 AMD Am386SE CPU
2.26.9 AMD Am386EM CPU
2.27 IBM 386 CPU
2.27.1 IBM 386SLC CPU
2.28 Chips & Technologies 386 CPU
2.28.1 Chips & Technologies Super386 38600DX CPU
2.28.2 Chips & Technologies 38605DX CPU
2.28.3 Chips & Technologies 38600SX CPU
2.29 IBM 386/486 hybrid CPU
2.29.1 IBM 486DLC CPU
2.29.2 IBM 486DLC2 CPU
2.29.3 IBM 486SLC CPU
2.29.4 IBM 486SLC2 CPU
2.29.5 IBM 486BLX CPU (Blue Lightning)
2.29.6 IBM 486BLX2 CPU (Blue Lightning)
2.29.7 IBM 486BLX3 CPU (Blue Lightning)
2.30 Cyrix 386/486 hybrid CPU
2.30.1 Cyrix Cx486DLC CPU
2.30.2 Cyrix Cx486SLC CPU
2.30.3 Cyrix Cx486SLC/e CPU
2.30.4 Cyrix Cx486SLC/e-V CPU
2.30.5 Cyrix Cx486DLC / Cx486SLC CPU incompatibilities
2.30.6 Cyrix Cx486DLC2 CPU
2.30.7 Cyrix Cx486SLC2 CPU
2.30.8 Cyrix Cx486DRx CPU
2.30.9 Cyrix Cx486SRx CPU
2.30.10 Cyrix Cx486DRx2 CPU
2.30.11 Cyrix Cx486SRx2 CPU
2.30.12 Cyrix Cx486DRu CPU
2.30.13 Cyrix Cx486SRu CPU
2.30.14 Cyrix Cx486DRu2 CPU
2.30.15 Cyrix Cx486SRu2 CPU
2.31 Texas Instruments 386/486 hybrid CPU
2.31.1 Texas Instruments TI486DLC CPU
2.31.2 Texas Instruments TI486SLC CPU
2.31.3 Texas Instruments TI486SXL-S-GA CPU (Potomac)
2.31.4 Texas Instruments TI486SXL-VS-GA CPU (Potomac)
2.31.5 Texas Instruments TI486SXL2-S-GA CPU (Potomac)
2.31.6 Texas Instruments TI486SXL2-VS-GA CPU (Potomac)
2.31.7 Texas Instruments TI486SXLC-PAF CPU (Potomac)
2.31.8 Texas Instruments TI486SXLC-V-PAF CPU (Potomac)
2.31.9 Texas Instruments TI486SXLC2-PAF CPU (Potomac)
2.31.10 Texas Instruments TI486SXLC2-V-PAF CPU (Potomac)
2.31.11 Texas Instruments announcements
2.32 Intel i80486 CPU
2.32.1 Intel i80486DX P4 CPU
2.32.2 Intel i80486SL CPU
2.32.3 Intel i80486DXL CPU
2.32.4 Intel i80486SX P23 CPU
2.32.5 Intel i80486SXL CPU
2.32.6 Intel i80486DX2 P24 CPU
2.32.7 Intel i80486DX4 P24C CPU
2.32.8 Intel i80486SX2 CPU
2.33 AMD Am486 CPU
2.33.1 AMD Am486DX CPU
2.33.2 AMD Am486DXL CPU
2.33.3 AMD Am486DXLV CPU
2.33.4 AMD Am486DX2 CPU
2.33.5 AMD Am486DXL2 CPU
2.33.6 AMD Am486DX4 CPU
2.33.7 AMD Am486SX CPU
2.33.8 AMD Am486SXLV CPU
2.33.9 AMD Am486SX2 CPU
2.33.10 AMD Am486SE CPU
2.33.11 AMD Am486DX4 SE CPU
2.33.12 AMD Am5x86 X5 CPU
2.34 IBM 80486 CPU
2.34.1 IBM 80486DX CPU
2.34.2 IBM 80486SX CPU
2.34.3 IBM 80486BLDX2 CPU (Blue Lightning)
2.35 IBM 5x86C CPU
2.36 Cyrix Cx486 CPU
2.36.1 Cyrix FasCache Cx486D CPU
2.36.2 Cyrix FasCache Cx486S CPU
2.36.3 Cyrix FasCache Cx486S/e CPU
2.36.4 Cyrix FasCache Cx486S-V CPU
2.36.5 Cyrix FasCache Cx486S2 CPU
2.36.6 Cyrix FasCache Cx486S2/e CPU
2.36.7 Cyrix FasCache Cx486S2-V CPU
2.36.8 Cyrix FasCache Cx486DX CPU
2.36.9 Cyrix FasCache Cx486DX-V33 CPU
2.36.10 Cyrix FasCache Cx486DX2 CPU
2.36.11 Cyrix FasCache Cx486DX2-V33 CPU
2.36.12 Cyrix FasCache Cx486DX2-V CPU
2.36.13 Cyrix FasCache Cx486DX4 CPU
2.36.14 Cyrix 5x86 CPU
2.37 Texas Instruments TI486 CPU
2.37.1 Texas Instruments TI486SXL-GA CPU (Potomac)
2.37.2 Texas Instruments TI486SXL-V-GA CPU (Potomac)
2.37.3 Texas Instruments TI486SXL2-GA CPU (Potomac)
2.37.4 Texas Instruments TI486SXL2-V-GA CPU (Potomac)
2.37.5 Texas Instruments TI486DX2 CPU
2.37.6 Texas Instruments TI486DX4 CPU
2.38 SGS-Thomson ST486 CPU
2.38.1 SGS-Thomson ST486DX2 CPU
2.39 UMC 486 CPU
2.39.1 UMC U5S CPU
2.39.2 UMC U5SD CPU
2.39.3 UMC U5SF CPU
2.39.4 UMC U5SLV CPU
2.39.5 UMC U5FLV CPU
2.39.6 UMC U486DX2 CPU
2.39.7 UMC U486SX2 CPU
2.40 Intel OverDrive CPU for Intel i80486 CPU
2.40.1 Intel i80486DX2 CPU for Intel i80486DX CPU (ODPR)
2.40.2 Intel i80486DX2 CPU for Intel i80486SX CPU (ODPR)
2.40.3 Intel i80486DX2 CPU for Intel i80486DX CPU (ODP)
2.40.4 Intel i80486DX2 CPU for Intel i80486SX CPU (ODP)
2.40.5 Intel i80486DX4 CPU for Intel i80486DX CPU, Intel i80486DX2 CPU (ODP)
2.40.6 Intel Pentium P24T CPU (ODP)
2.40.7 Intel Pentium P24CT CPU (ODP)
2.41 Cyrix Overdrive CPU
2.42 Intel Pentium CPU
2.42.1 Intel Pentium P5 CPU
2.42.2 Intel Pentium P54C CPU
2.43 Intel OverDrive CPU for Intel Pentium CPU
2.43.1 Intel Pentium P54M CPU
2.43.2 Intel Pentium OverDrive CPU
2.44 AMD K5 CPU (K86 series)
2.44.1 AMD 5k86 K5 CPU (K86 series)
2.44.2 AMD 5k86 SSA/5 CPU (K86 series)
2.45 Cyrix 586 CPU
2.45.1 Cyrix Cx5x86 CPU
2.46 NexGen Nx586/Nx587 CPU chipset
2.47 Intel Pentium Pro P6 CPU
2.47.1 Intel Pentium Pro P6L CPU
2.48 Intel OverDrive CPU
2.48.1 Intel OverDrive P6T CPU
2.49 IBM 6x86 CPU
2.49.1 IBM 6x86 CPU
2.49.2 IBM 6x86L CPU
2.50 Cyrix 6x86 CPU
2.51 NexGen Nx686 CPU
2.52 Intel MMX technology
2.53 Intel Pentium/MMX P55C CPU
2.54 Intel Mobile Pentium/MMX CPU
2.55 Intel Pentium/MMX OverDrive CPU
2.56 Intel Pentium II CPU
2.56.1 Intel Pentium II CPU
2.56.2 Intel Pentium II CPU
2.56.3 Intel Pentium Celeron CPU
2.56.4 Intel Mobile Pentium II CPU
2.56.5 Intel Pentium II Xeon CPU
2.56.6 Intel Katmai CPU
2.56.7 Intel announcements
2.57 AMD K6 CPU
2.57.1 AMD K6-2 CPU
2.57.2 AMD announcements
2.58 IBM 6x86MX CPU
2.59 Cyrix 6x86MX CPU
2.60 Centaur IDT WinChip C6 CPU
2.60.1 Centaur IDT WinChip C6+ CPU
2.60.1 Centaur IDT WinChip-2-3D C6+ CPU
2.61 Multi-Media CPU
2.61.1 Cyrix MediaGX CPU
2.62 DEC Alpha CPU
2.62.1 DEC DECchip-210 Alpha CPU
2.62.2 DEC DECchip-211 Alpha CPU
2.62.3 DEC DECchip-212 Alpha CPU
2.63 MIPS CPU
2.63.1 MIPS R4000 CPU
2.63.2 MIPS R4200 CPU
2.63.3 MIPS R4400 CPU
2.63.4 MIPS Orion R4600 CPU
2.63.5 MIPS R10000 CPU
2.63.6 MIPS announcements
2.64 IBM, Motorola PowerPC CPU
2.64.1 IBM, Motorola PowerPC 401 CPU
2.64.2 IBM, Motorola PowerPC 601 CPU
2.64.3 IBM, Motorola PowerPC 602 CPU
2.64.4 IBM, Motorola PowerPC 603 CPU
2.64.5 IBM, Motorola PowerPC 603e CPU
2.64.6 IBM, Motorola PowerPC 604 CPU
2.64.7 IBM, Motorola PowerPC 604e CPU
2.64.8 IBM, Motorola PowerPC 615 CPU
2.64.9 IBM, Motorola PowerPC 620 CPU
2.64.10 IBM, Motorola PowerPC 630 CPU
2.64.11 IBM, Motorola PowerPC 750 CPU
2.65 Sun Sparc CPU
2.66 HP PA CPU (Precision Architecture)
2.67 Java CPU
2.67.1 Sun microJava 701 CPU
2.68 Motorola CPU
2.68.1 Motorola MC6800 CPU
2.68.2 Motorola MC6802 CPU
2.68.3 Motorola MC68HC11 CPU
2.68.4 Motorola MC6809 CPU
2.68.5 Motorola MC68000 CPU
2.68.6 Motorola MC68008 CPU
2.68.7 Motorola MC68302 CPU
2.68.8 Motorola MC68010 CPU
2.68.9 Motorola MC68340 microprocessor
2.68.10 Motorola MC68020 CPU
2.68.11 Motorola MC68030 CPU
2.68.12 Motorola MC68040 CPU
2.68.13 Motorola MC68LC040 CPU
2.68.14 Motorola MC68040V CPU
2.68.15 Motorola MC68050 CPU
2.68.16 Motorola MC68060 CPU

3 NPX (Numerical Processor eXtension)
3.1 Introduction
3.2 Intel i8087 NPX
3.3 Intel i80287 NPX
3.4 AMD Am80287 NPX
3.4.1 AMD Am80C287 NPX
3.4.2 AMD Am80EC287 NPX
3.5 Cyrix Cx287 NPX
3.6 Intel i80187 NPX
3.7 Intel i80287XL NPX
3.8 Cyrix FasMath Cx82S87 NPX
3.9 IIT IIT-2C87 NPX
3.10 Intel i80387 NPX
3.10.1 Intel i80387 NPX
3.10.2 Intel i80387DX NPX
3.10.3 Intel i80387SX NPX
3.10.4 Intel i80387SL Mobile NPX
3.10.5 Intel i80X87SL Mobile NPX
3.11 Chips & Technologies SuperMath 38700 NPX
3.11.1 Chips & Technologies SuperMath 38700DX NPX
3.11.2 Chips & Technologies SuperMath 38700SX NPX
3.12 Cyrix 80387 NPX
3.12.1 Cyrix FasMath Cx83D87 NPX
3.12.2 Cyrix FasMath Cx387+ NPX
3.12.3 Cyrix FasMath EMC87 NPX
3.12.4 Cyrix FasMath 83S87 NPX
3.12.5 Cyrix Cx387DX NPX
3.12.6 Cyrix Cx387SX NPX
3.12.7 Cyrix Cx387 NPX announcements
3.13 IIT IIT-3C87 NPX
3.13.1 IIT IIT-3C87 NPX
3.13.2 IIT IIT-3C87SX NPX
3.13.3 IIT IIT-XC87DLX2 NPX
3.14 ULSI Math*Co 83C87 NPX
3.15 ULSI Math*Co 83S87 NPX
3.16 Weitek Abacus 1167 NPX
3.17 Weitek Abacus 3167 NPX
3.18 RISE 80387 NPX
3.19 Symphony Laboratories 80387 NPX
3.20 Cyrix Cx4C87DLC NPX
3.21 IIT IIT-4C87 NPX
3.21.1 IIT IIT-4C87DLC NPX
3.21.2 IIT IIT-4C87 NPX announcements
3.22 Intel i80487 NPX
3.22.1 Intel i80487SX P23N NPX
3.22.2 Intel i80487 NPX
3.23 Cyrix Cx487S NPX
3.24 Weitek Abacus 4167 NPX

Credits


1 Introduction

1.1 Identification

Manufacturer: name and/or logo.
Part number.
Revision number, step level.
Date: often the week number and the year of manufacturing.

Memory chips: capacity: 64, 256 kbit,
1, 4, 16, 64 Mbit,
speed: 10, 15, 20, 40, 60, 70, 80, 100, 120, 150 ns.

Orientation: indicated by a hole or a dot; from this indication the pin
numbering starts contra clock-wise with number 1.

For microprocessors at boot the chip mask revision number is often left in one
of the control registers.

In the newer SL enhanced Intel i80486 CPUs (if bit 21 in EFLAGS can be
toggled) and the Intel Pentium CPUs a CPUID instruction is available:
EAX=0: EAX: highest input value recognized by CPUID
EBX-EDX: vendor ID string: Intel: "GenuineIntel"
AMD: "AuthenticAMD"
Cyrix: "CyrixInstead"
NexGen: "NexGenDriven"
UMC: "UMC UMC UMC "
EAX=1: EAX: bit 0-3: step level
bit 4-7: model
bit 8-11: family: 4: 486,
5: Pentium
bit 12-31: reserved
EBX-ECX: reserved
EDX (feature bits): bit 0: on-chip FPU
bit 1-6: I/O Breakpoints available
Page Size extensions (single-level page
table with 4 Mbyte pages)
Time Stamp Counter available (RDTSC)
Machine Specific Registers available
(RDMSR/WRMSR)
bit 7: Machine Check Exception
bit 8: CMPXCHG8B instruction
bit 9-31: reserved


1.2 Packages

DIP (Dual In-line Package): o o o o o o o o

o o o o o o o o

CERDIP (CERamic Dual In-line Package).

PQFP (Plastic Quad Flat Package): surface mounted.
SQFP (Shrink Quad Flat Package): surface mounted, thermally enhanced.
MQFP (Metal Quad Flat Package).

PLCC (Plastic Leaded Chip Carrier).

PGA (Pin Grid Array): o o o o o o o o
o o o o o o o o
o o o o
o o o o
o o o o
o o o o
o o o o o o o o
o o o o o o o o

SPGA (Pin Grid Array).
CPGA (Ceramic Pin Grid Array).
PPGA (Plastic Pin Grid Array).

SEC module (Single Edge Contact): consists of a PCB containing the processor
chip and the level 2 cache chips.

ZIF sockets (Zero Insertion Force) have a handle to fasten and loosen the chip
to and from its socket.

BGA (Ball Grid Array):
The BGA system consists of balls on the chip package that fit into grips on
the socket.
Two new systems are developed by and available from Aries Electronics, Inc.:
http://www.arieselec.com/
BallNest provides a four-fingered "nest" for each ball termination of the
device to be socketed. On top of the BGA device a socket lid must be placed
to hold it down. The BallLock system grips the balls of the BGA device,
eliminating the need for a lid. A ZIF (Zero Insertion Force) version of the
BGA socket is being worked on.

ZIP (Zigzag In-line Package): o o o o o o o o
o o o o o o o o

DRAM (Dynamic Random Access Memory): 4116 16 k x 1 (1980),
4164 64 k x 1 (1982),
41256 256 k x 1 (1984),
411000 1 M x 1 (1987, 1988).

SIMM (Single In-line Memory Module) (Wang): contains a complete RAM bank.
MAC SIMMs are only 8 bits wide; they don't contain a parity bit.
However, there are Personal Computers around in which parity checking can be
disabled, that can operate with 8 bit SIMMs.

9-chip SIMM: 9 chips of 1 bit wide
8-chip SIMM: 8 chips of 1 bit wide (MAC)
3-chip SIMM: 2 chips of 4 bits wide and 1 chip of 1 bit wide
3 chips of 3 bits wide
2-chip SIMM: 2 chips of 4 bits wide (MAC)

If the correct refresh is supplied, SIMMs with a different number of chips and
different speed can be used together.

SIP (Single In-line Package): contains a complete RAM bank.

The orientation of SIMMs and SIPs is indicated by a hole. Starting from this
indication the numbering of the pins starts with number 1. Apart from the pins
there is no difference at all between SIMMs and SIPs.

The normal SIMMs and SIPs have 30 pads/pins. There are also 36 pin SIMMs and
SIPs. The extra pins are used for speed detection by the motherboard.

There are also 72 pin SIMMs. These are 32 bits and 4 parity bits wide. 4 pins
are assigned for speed detection. They are mostly used in 486 class and higher
Personal Computers.
Capacity: 1, 2, 4, 8, 16, 32 Mbyte.

DIMM (Dual In-line Memory Module): 64 bit memory module.
They have 168 pads. They can only be found in the newer Pentium class Personal
Computers.

Memory banks, consisting of 1, 2, or 4 sockets, should always be filled
completely. The number of sockets in a bank depends on the width of the memory
module and the width of the processor's address bus. For example, a bank in a
486 class motherboard (32 bit address bus) might need four 8 bit SIMMs, or a
single 32 bit SIMM.

EDO RAM (Extended Data Output): faster access method.
This can only be found in the newer Pentium class Personal Computers.

SDRAM (Synchronous DRAM): clock synchronized with the CPU busses.
This can only be found in the newer Pentium class Personal Computers.


1.3 Semiconductor processes

RTL (Resistor-Transistor Logic): SSI (Small Scale Integration).

DTL (Diode-Transistor Logic): SSI.

TTL (Transistor-Transistor Logic) (Texas Instruments, 1965): bipolar,
SSI, MSI (Medium Scale Integration), LSI (Large Scale Integration).

7400 series: 0 - 70 C.
5400 series: -55 - 125 C (military).

5400, 7400: 10 ns propagation time,
54L00, 74L00: Low power: higher resistances, less dissipation: longer
propagation time,
54H00, 74H00: High power: lower resistances, more dissipation: less
sensitivity for noise,
54S00, 74S00: Schottky-clamped: faster switching by using Schottky diodes
to prevent the transistors from saturation,
54LS00, 74LS00: Low power, Schottky-clamped,
54AS00, 74AS00: Advanced Schottky: faster switching, less dissipation,
54ALS00, 74ALS00: Advanced Low power Schottky.

I2L (Integrated Injection Logic) (1972): bipolar,
LSI, VLSI (Very Large Scale Integration).

Vcc: 0.8 V.
Propagation time: 20 - 50 ns.
Speed-power: 0.5 pJ.

ECL (Emitter Coupled Logic, Current Mode Logic): bipolar.

Propagation time: 0.5 - 2 ns.
Dissipation: 3 - 10 times higher than TTL.

MOS (Metal Oxide Semiconductor): FET (Field-Effect Transistors).

Maximum frequency: 25 MHz.

PMOS (Positive-channel MOS): LSI, VLSI.

NMOS (Negative-channel MOS): LSI, VLSI.

Faster than PMOS.

HMOS (High performance n-channel MOS): LSI, VLSI.

CMOS (Complementary MOS): LSI, VLSI, ULSI (Ultra Large Scale Integration).

Better current management combining n- and p-channels.
Originally slower than NMOS.

CMOS-SOS (Silicon On Sapphire).

Low capitance.
100 MHz.

Developed by military for radiation hardness in space and tactical/strategic
nuclear warfare environments.

For a long time 0.6 micron geometries were thought to be a limit imposed by
the electron microscopes used for mask alignment, but then the X-ray
lithography was invented.
Now, the EUV LLC (EUV Limited Liability Company), consisting of Intel, AMD,
and Motorola, and the VNL (Virtual National Laboratory), are working on an
advanced lithography research project EUV (Extreme Ultra Violet), which will
allow industries to etch circuit lines smaller than 0.1 micron widths. The
EUV technology uses mirrors instead of lenses for the mask light exposure.

In September 1997 IBM started manufacturing chips with copper metal layers
instead of aluminium. Copper is a better conductor, and allows for circuit
lines smaller than 0.1 micron widths. Corrosion of the silicium by the copper
is avoided by using a fusion barrier sealer in between.


1.4 JEDEC (Joint Electronic Device Engeneering Council)

JEDEC was first known for their DIP definitions for memory chips.

JEDEC has suggested a new standard of 3.3 V for all electronic components,
including CPUs. CPUs operating at 3.3 V consume less than 50 % of the power
of their 5 V equivalents. Intel currently uses a manufacturing process with a
resolution of 0.8 micron, but is starting production with a 0.6 micron
process. This produces chips that can only operate reliably at 3.3 V, which
means that all its future CPUs are likely to operate only at this lower
voltage.


1.5 Manufacturers

1.5.1 Intel

In July 1997 Intel acquired Chips & Technologies.

Intel fax-back service: 1-800-628-2283.
European Centre: +44 (0) 1793-432509.

Intel WWW server: www.intel.com
Intel FTP site: ftp.intel.com

Intel European Centre: +44 (0) 1793-431155.
Resellers: +44 (0) 1793-432955.


1.5.2 AMD (Advanced Micro Devices)

In 1996 AMD acquired NexGen.

AMD European Corporate Applications Technical Hot-Line Support:
euro...@amd.com
euro...@amd.com

AMD WWW server: www.amd.com
AMD FTP site: ftp.amd.com


1.5.3 IBM (International Bussiness Machines)

IBM WWW server: www.ibm.com
www.chips.ibm.com


1.5.4 Chips & Technologies

Chips & Technologies has dropped its development of X86 clones.

Acquired by Intel in July 1997.


1.5.5 Cyrix

Acquired by National Semiconductor in July 1997.

Cyrix WWW server: www.cyrix.com

Cyrix fax-back service: 1-800-46-CYRIX (1-800-462-9749).


1.5.6 Texas Instruments

TI FTP site: ftp.ti.com


1.5.7 UMC


1.5.8 NexGen

Acquired by AMD in 1996.

NexGen WWW server: www.nexgen.com


1.5.9 IIT (Integrated Information Technology)


1.5.10 Motorola

Motorola WWW server: www.mot.com


1.5.11 Apple

Apple WWW server: www.apple.com


1.5.12 HP

HP WWW server: www.hp.com
HP FTP server: ftp.hp.com


1.5.13 DEC (Digital Equipment Corporation)

DEC WWW server: www.dec.com


1.5.14 Renaissance Microsystems Inc.

Developping PowerPC clones.


1.5.15 IDT (Integrated Device Technology)

IDT WWW server: www.idt.com
Centaur Technology WWW server: www.centtech.com


1.6 References

Andrew S. Tanenbaum: Structured Computer Organization (Prentice-Hall)
A.J. van de Goor: Computer Architecture and Design (Addison-Wesley)
William Stallings: Computer Organization and Architecture (MacMillan)
John L. Hennessy & David A. Patterson: Computer Architecture, a Quantitative
Approach (Morgan Kaufman)
Norbert Juffa: Performance Comparison Intel 386DX, Intel RapidCAD, C&T 38600DX,
Cyrix 486DLC (USENET News)
Norbert Juffa: Everything you always wanted to know about math coprocessors
(USENET News)

Chip Directory, by Jaap van Ganswijk:
http://www.xs4all.nl/~ganswijk/chipdir/

Chronology of Events in the History of Microcomputers, by Ken Polsson:
http://www.islandnet.com/~kpolsson/comphist.htm

CPU Info Center:
http://infopad.eecs.berkeley.edu/CIC/

Intel Secrets; What Intel doesn't want you to know, by Robert Collins:
http://www.x86.org/
FTP: ftp.x86.org /pub/x86/

Internet Microcontroller/Microprocessor/CPU Directory:
http://www.cera.com/micro.htm

MicroDesign Resources:
http://www.chipanalyst.com/

PC Hardware Links, by Chris Hare:
http://www.erols.com/chare/

Tom's Hardware Guide:
http://sysdoc.pair.com/


Compiled, Copyright 1993 - 1998, by A. Offerman. Permission to use, copy, or
distribute this document in a non-commercial way for non-commercial use is
hereby granted, provided that this copyright and permission notice appear in
all copies. All other rights reserved.

This document is provided "as is" without expressed or implied warranty.

The specific products and their respective manufacturers are not to be taken
as endorsements of, nor commercials for, the manufacturer.

Aad Offerman

unread,
Jul 27, 1998, 3:00:00 AM7/27/98
to
Archive-name: pc-hardware-faq/chiplist/part3
Last-modified: 1998/06/14
Version: 9.9.5


2.32 Intel i80486 CPU

Intel i80386 CPU upward instruction compatible.
Extra instructions.

8 kbyte unified cache: write-through, 4-way set-associative, 128 sets,
16 bytes per cache line, 4 write buffers,
only invalidation of a complete cache line,
96 % hit rate.

32 bit internal data bus.
32 bit external data bus.
32 bit address bus.

Execution unit:
5-stage pipeline,
barrel shifter,
branch taken / not taken prediction (BTB: Branch Target Buffer).

Burst mode memory access: first access: 2 clock cycles,
every next access: 1 clock cycle.


2.32.1 Intel i80486DX P4 CPU

Build-in FPU (Floating Point Unit).

April 1989.

20 MHz: CMOS.
25 MHz: 2600 mW, CHMOS IV, iCOMP 122, no longer available.
33 MHz: 3500 mW, CHMOS IV.
50 MHz: June 1991, 3875 mW, CHMOS V.

Upgrading: Intel i80486DX2 CPU (ODPR), Intel OverDrive CPU (ODP:
Intel i80486DX2 CPU), Intel i80486DX4 CPU (ODPR),
Intel OverDrive CPU (ODP: Intel i80486DX4 CPU), Intel OverDrive CPU
(ODPR: Intel Pentium CPU with Intel i80486DX CPU bus interface),
Intel OverDrive CPU (ODP: Intel Pentium CPU).

Package: 168 pin PGA (Pin Grid Array).

1.185E6 transistors.
Die size: 165 mm2.

From June 1993 (Intel i80486DX-S CPU):

SL Enhanced.

33 MHz: iCOMP 166.
50 MHz: iCOMP 249.

CPUID: family = 0x4, model = 0x1.

From June 1993:

SL Enhanced.
Low power: 3.3 V.

33 MHz.

No longer available from second quarter 1995.

ID (25 - 33 MHz, CMOS IV):
step level A0, A1: DH = 0x04 (family ID), DL = 0x00 (model ID, revision),
step level B2-B6: DH= 0x04 (family ID), DL = 0x01 (model ID, revision),
step level C0: DH = 0x04 (family ID), DL = 0x02 (model ID, revision),
step level C1: DH = 0x04 (family ID), DL = 0x03 (model ID, revision),
step level D0: DH = 0x04 (family ID), DL = 0x04 (model ID, revision).
ID (50 MHz, CMOS V):
step level cA2, cA3: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level cB0, cB1: DH = 0x04 (family ID), DL = 0x11 (model ID, revision),
step level cC0: DH = 0x04 (family ID), DL = 0x13 (model ID, revision),
step level aA0, aA1 (SL Enhanced): DH = 0x04 (family ID), DL = 0x14
(model ID, revision),
step level aB0 (SL Enhanced): DH = 0x04 (family ID), DL = 0x15 (model ID,
revision).


2.32.2 Intel i80486SL CPU

Intel i80486DX CPU with extra features:
DRAM controller,
ISA (Industry Standard Architecture) controller,
local PI-bus controller (Peripheral Interconnect),
power management: SMM (System Management Mode).
Static core.

25 Mhz.
33 MHz.

Not Intel i80486DX CPU pin compatible.
196 pin PQFP (Plastic Quad Flat Package).

Technology: CMOS.

From June 1993 replaced by Intel i80486DX-S CPU.

ID: step level A: DH = 0x04 (family ID), DL = 0x40 (model ID, revision).


2.32.3 Intel i80486DXL CPU

Intel i80486DX CPU with extra features: SMM (System Management Mode),
stop clock,
power saving features.
Static core.

Technology: CMOS.


2.32.4 Intel i80486SX P23 CPU

No build-in FPU (Floating Point Unit):
Intel i80486DX CPU die with FPU disabled,
currently FPU not implemented (resulting in a smaller chip, plastic package).

One extra pin assigned to allow an Intel i80487SX NPX to disable this CPU.
Not Intel i80486DX CPU upward pin compatible.
Package: 168 pin PGA (Pin Grid Array).

April 1991.

16 MHz: 1991, no longer available.
20 MHz: 1991, iCOMP 78, no longer available.
25 MHz: 1991, iCOMP 100 (per definition).
33 MHz: 1991.

Upgrading: Intel i80486DX CPU (ODPR: Intel i80486DX CPU with
Intel i80486SX CPU pin layout), Intel i80486DX2 CPU (ODPR:
Intel i80486DX2 CPU with Intel i80486SX CPU pin layout),
Intel OverDrive CPU (ODP: Intel i80486DX2 CPU), Intel i80486DX4 CPU
(ODPR: Intel i80486DX4 CPU with Intel i80486SX CPU pin layout),
Intel OverDrive CPU (ODP: Intel i80486DX4 CPU), Intel OverDrive CPU
(ODPR: Intel Pentium CPU with Intel i80486SX CPU bus interface),
Intel OverDrive CPU (ODP: Intel Pentium CPU).

Package: 168 pin PGA (Pin Grid Array),
208 pin PQFP (Plastic Quad Flat Package).

Technology: CMOS.
0.9E6 transistors.

From June 1993 (Intel i80486SX-S CPU):

SL Enhanced.

25 MHz: iCOMP 100 (by define).
33 MHz: iCOMP 136.

CPUID: family = 0x4, model = 0x2.

From June 1993:

SL Enhanced.
Low Power: 3.3 V.

25 MHz.
33 MHz.

ID: step level A0: DH = 0x04 (family ID), DL = 0x20 (model ID, revision),
step level B0: DH = 0x04 (family ID), DL = 0x22 (model ID, revision),
step level cA0: DH = 0x04 (family ID), DL = 0x27 (model ID, revision),
step level cB0: DH = 0x04 (family ID), DL = 0x28 (model ID, revision),
step level D: DH = 0x04 (family ID), DL = 0x23 (model ID, revision),
step level E: DH = 0x04 (family ID), DL = 0x2A (model ID, revision),
step level gAx: DH = 0x04 (family ID), DL = 0x24 (model ID, revision),
step level aA0, aA1: DH = 0x04 (family ID), DL = 0x2A (model ID,
revision),
step level aB0, aC0: DH = 0x04 (family ID), DL = 0x2B (model ID,
revision).


2.32.5 Intel i80486SXL CPU

Intel i80486SX CPU with extra features: SMM (System Management Mode),
stop clock,
power saving features.
static core.

Technology: CMOS.


2.32.6 Intel i80486DX2 P24 CPU

Clock doubled version of the Intel i80486DX CPU.
Intel i80486DX CPU pin compatible.

March 1992.

20/40 MHz.
25/50 MHz: 4000 mW.
33/66 MHz: 4875 mW.

G4C, G4S.

Technology: CMOS.
1.2E6 transistors.
Die size: 230 mm2.

From June 1993 (Intel i80486DX2-S CPU):

SL Enhanced.

20/40 MHz: SQFP (Shrink Quad Flat Package).
25/50 MHz: iCOMP 231.
33/66 MHz: iCOMP 297.

CPUID: family = 0x4, model = 0x3.

From Nov 1993:

SL Enhanced.
Low power: 3.3 V.

20/40 MHz.
25/50 MHz.

From October 1994 (P24D) (not marketed, P24CT OverDrive Processor Pretest Kit
for Intel Verification Program (OEM)):

Write-back cache.
Upward pin compatible.
Performance increase: 15 %.

25/50 MHz.
33/66 MHz.

No longer available from fourth quarter 1995.

ID: step level A0-A2: DH = 0x04 (family ID), DL = 0x32 (model ID, revision),
step level B1: DH = 0x04 (family ID), DL = 0x33 (model ID, revision),
step level aA0, aA1 (SL Enhanced): DH = 0x04 (family ID), DL = 0x34
(model ID, revision),
step level aB0, aC0 (SL Enhanced): DH = 0x04 (family ID), DL = 0x35
(model ID, revision),
step level A (write-back): DH = 0x04 (family ID), DL = 0x36 (model ID,
write-through), DL = 0x7X (model ID,
write-back).


2.32.7 Intel i80486DX4 P24C CPU

Clock tripled version of the Intel i80486DX CPU.
Selection of doubling/tripling by a pin on the chip (CLKMUL: 0, 1). Connecting
this pin with the BREQ pin makes the core running at 2.5 times the external
speed (not implemented yet).
Intel i80486DX CPU upward pin compatible.

5 V external, 3.3 V internal: if the motherboard does not provide the 3.3 V
power to the CPU, the CPU can be installed using
a special socket wired to the 3.3 V output of
your PSU (Power Supply Unit); in either case
another PSU providing the 3.3 V is needed.

3.3 V.

16 kbyte cache.

25/75 MHz max (A80486DX475): 3.3 V, March 1994, iCOMP 319.
33/100 MHz max (A80486DX4100): 51 SPECint92, 27 SPECfp92, 3.3 V, March 1994,
iCOMP 435.
Production cancelled for a few months from September 1994 in favor of
Intel Pentium CPUs.

Power consumption: 4 W typical.

SL Enhanced Intel i80486DX CPU pin compatible.
Package: 168 pin PGA (Pin Grid Array).

Extra integer multiplier: 5 cycle 16 x 16 multiply.

Package: 168 pin PGA (Pin Grid Array),
208 pin SQFP (Shrink Quad Flat Package).

Technology: 4-layer metal, 0.6 micron biCMOS/CHMOS.
1.6E6 transistors.
Die size: 87 mm2.

ID: step level A: DH = 0x04 (family ID), DL = 0x8X (model ID, revision).

CPUID: step level A: family = 0x4, model = 0x8.

From October 1994 (Intel i80486DX4WB CPU): write-back cache.
Code: &EW.

Intel i80486DX4 P54LM CPU: notebooks,
2.5 - 2.9 V,
90 MHz,
100 MHz.


2.32.8 Intel i80486SX2 CPU

Clock doubled version of the Intel i80486SX CPU.

SL Enhanced.

25/50 MHz: March 1994, iCOMP 180.
33/66 MHz.

ID: step level aC0: DH = 0x04 (family ID), DL = 0x5B (model ID, revision).


2.33 AMD Am486 CPU

Originally same core and microcode as Intel i80486 CPUs; currently an own
implementation. In between there were CPUs with recompiled 486 microcode.
Intel i80486 CPU instruction compatible.

All current Enhanced AMD processors support the CPUID instruction.


2.33.1 AMD Am486DX CPU

Intel i80486DX CPU instruction/pin compatible.

Cache: 8 kbyte, write-through.

April 1993.

25 MHz.
33 MHz: 8-33 MHz, 1993.
40 MHz: 8-40 MHz, 1993.

Technology: CMOS.
1E6 transitors.
Die size: 89 mm2.

ID: DH = 0x04 (family ID), DL = 0x1X (model ID, revision),
DH = 0x04 (family ID), DL = 0x12 (model ID, revision).


2.33.2 AMD Am486DXL CPU

Low power version of the AMD Am486DX CPU.

October 1993.

40 MHz.

Technology: CMOS.

ID: DH = 0x04 (model ID), DL = 0x12 (model ID, revision).


2.33.3 AMD Am486DXLV CPU

Low power (SMM: System Management Mode), low voltage (3.0 V) version of the
AMD Am486DX CPU.
Static core.

October 1993.

33 MHz: 0-33 MHz, 1993.

Technology: CMOS.

ID: DH = 0x04 (model ID), DL = 0x12 (model ID, revision).


2.33.4 AMD Am486DX2 CPU

Clock doubled version of the AMD Am486DX CPU.

April / October 1993.
From November 1994: 3.3 V.

25/50 MHz: 1993.
33/66 MHz: heatsink required.
40/80 MHz: September 1994, heatsink required.
50/100 MHz.
Some 3.3 V, 66, 80 MHz items are DX4 parts that failed Q.C. at 100 MHz
(Malaysia, fab number 25253).

Technology: CMOS.

ID: DH = 0x04 (family ID), DL = 0x3X (model ID, revision).

AMD Enhanced Am486DX2 CPU:

cache: write-through / write-back,

33/66 MHz,
40/80 MHz,
50/100 MHz,

DX register & CPUID: 0x43X (write-through cache),
0x47X (write-back cache).


2.33.5 AMD Am486DXL2 CPU

Clock doubled version of the AMD Am486DXL CPU.
Low power (SMM: System Management Mode).

AMD core/microcode.

33/66 MHz.
40/80 MHz.

Technology: CMOS.

ID: DH = 0x04 (family ID), DL = 0x32 (model ID, revision).


2.33.6 AMD Am486DX4 CPU

Clock tripled version of the AMD Am486DX CPU.
Intel i80486DX4 CPU pin compatible.
Selection of doubling/tripling by a pin on the chip.

8 kbyte cache: write-through.

33/100 MHz: 3.3 V, September 1994, heatsink + fan required.
40/120 MHz: 3.3 V.

Technology: 3-layer metal, 0.5 micron CMOS.

ID: DH = 0x04 (family ID), DL = 0x3X (model ID, revision),
DH = 0x04 (family ID), DL = 0x32 (model ID, revision).

AMD Am80486DX4-xxxNT8T CPU.
AMD Am80486DX4-xxxNV8T CPU.

Enhanced AMD Am486DX4 CPU (AMD Am80486DX4-xxxSV8B CPU):
SL Enhanced,
write-through / write-back cache,
3.3 V,

25/75 MHz,
33/100 MHz,
40/120 MHz,

package: 169 pin PGA (Pin Grid Array),
208 pin SQFP,

AMD Enhanced Am486DX4 CPU (write-through cache): DX register & CPUID: 0x48x,
AMD Enhanced Am486DX4W CPU (write-back cache): DX register & CPUID: 0x49x,

label: A 80486DX4-100 SV8B:
S: SMM (System Management Mode),
N: standard,
V: low power,
_: standard,
8: 8 kbyte cache,
B: write-back cache,
T: write-through cache.


2.33.7 AMD Am486SX CPU

Intel i80486SX CPU instruction/pin compatible.

AMD microcode.

July 1993.

33 MHz: 1993.
40 MHz: 1993.

Technology: CMOS.


2.33.8 AMD Am486SXLV CPU

Low power (SMM: System Management Mode), low voltage (3.0 V) version of the
AMD Am486SX CPU.
Static core.

AMD microcode.

July 1993.

33 MHz.

Technology: CMOS.


2.33.9 AMD Am486SX2 CPU

Clock doubled version of the AMD Am486SX CPU.

25/50 MHz: February 1994.
33/66 MHz: April 1994.


2.33.10 AMD Am486SE CPU

Embedded static version of the AMD Am486SX CPU.

25 MHz: 1995.
33 MHz: 1995.

Package: CGM168.

AMD Embedded Processors E86 Family.


2.33.11 AMD Am486DX4 SE CPU

Embedded static version of the AMD Am486DX4 CPU.

40/120 MHz.

AMD Embedded Processors E86 Family.


2.33.12 AMD Am5x86 X5 CPU

Clock quadrupled Enhanced 486.
SL Enhanced Intel i80486DX2 CPU (P24D) pin compatible.

16 kbyte cache: write-through / write-back.

33/133 MHz (AMD Am5x86-P75, AMD 486X5-133): November 1995.
40/160 MHz.

3.3 V, 3.45 V.

Technology: 35 micron CMOS.
Die size: 43 mm2.

DX register & CPUID: 0x04EX (write-through),
0x04FX (write-back).

Label: Amd 5x86-P75 ADW:
A: PGA (Pin Grid Array),
S: SQFP,
D: 3.45 +- 0.15 V,
F: 3.3 +- 0.15 V,
W: case temperature 55 C,
Y: 75 C,
Z: 85 C.


2.34 IBM 80486 CPU

Intel i80486 CPU instruction compatible.


2.34.1 IBM 80486DX CPU

Intel i80486DX CPU instruction/pin compatible.

8 kbyte cache.

Technology: CMOS.


2.34.2 IBM 80486SX CPU

Intel i80486SX CPU instruction/pin compatible.

16 kbyte cache.

Technology: CMOS.


2.34.3 IBM 80486BLDX2 CPU (Blue Lightning)

33/66 MHz: Cyrix FasCache Cx486DX2-V-66 CPU.
40/80 MHz: Cyrix FasCache Cx486DX2-V-80 CPU.

ID: DH = 0xA4 (family ID), DL = 0x80 (model ID, revision).


2.35 IBM 5x86C CPU

Cyrix 5x86 CPU.

25/75 MHz.
IBM265x86-3V3100GB: 33/100 MHz, package: PGA (Pin Grid Array).
IBM265x86-3V3100QB: 33/100 MHz, package: PQFP (Plastic Quad Flat Package).


2.36 Cyrix Cx486 CPU

2.36.1 Cyrix FasCache Cx486D CPU

Intel i80486 CPU instruction compatible, no build-in FPU (Floating Point
Unit).
Can piggy-back a Cyrix Cx487S NPX.

2 kbyte cache: write-back.

Intel i80486SX CPU upward pin compatible.

On-chip ventilator.

40 MHz: 1993.

Technology: CMOS.

Cyrix M5 CPU.

ID: DH = 0x00 (family ID), DL = 0x05 (model ID).


2.36.2 Cyrix FasCache Cx486S CPU

Intel i80486 CPU instruction compatible, no build-in FPU (Floating Point
Unit).
Low Power: SMM (System Management Mode).
Static core.

2 kbyte cache: write-back.

Intel i80486SX CPU upward pin compatible.

May 1993.

33 MHz.
40 MHz: 1993.
50 MHz.

Technology: CMOS.

Cyrix M5 CPU.

ID: DH = 0x00 (family ID), DL = 0x05 (model ID).

DIR0 register: 0x10.


2.36.3 Cyrix FasCache Cx486S/e CPU

Low power (SMM: System Management Mode) version of the
Cyrix FasCache Cx486S CPU.
Static core.

DIR0 register: 0x12.


2.36.4 Cyrix FasCache Cx486S-V CPU

Low voltage (3.3 V) version of the Cyrix FasCache Cx486S CPU.

May 1993.

25 MHz.
33 MHz.

Technology: CMOS.

DIR0 register: 0x10.


2.36.5 Cyrix FasCache Cx486S2 CPU

Clock doubled version of the Cyrix FasCache Cx486S CPU.

October 1993.

20/40 MHz.
25/50 MHz.

Technology: CMOS.

DIR0 register: 0x11.


2.36.6 Cyrix FasCache Cx486S2/e CPU

Low power (SMM: System Management Mode) version of the
Cyrix FasCache Cx486S2 CPU.
Static core.

DIR0 register: 0x13.


2.36.7 Cyrix FasCache Cx486S2-V CPU

Low voltage (3.3 V) version of the Cyrix FasCache Cx486S2 CPU.

October 1993.

20/40 MHz.
25/50 MHz.

Technology: CMOS.

DIR0 register: 0x11.


Cyrix FasCache Cx486DX/Cx486DX2 CPU FP bug: when a register load instruction
is followed by an instruction that clears the FP status register (FCLEX), and
the memory location being referenced is not in the CPU's internal cache, the
external memory bus cycle is aborted by the FCLEX instruction and the register
is not loaded properly.
Since this code sequence is very unlikely to occur in any software, the bug
will probably not be fixed at all.

2.36.8 Cyrix FasCache Cx486DX CPU

Intel i80486DX instruction compatible, FPU (Floating Point Unit).
Low Power: SMM (System Management Mode).
Static core.

8 kbyte cache: write-through / write-back.

Intel i80486DX CPU upward pin compatible.

September 1993.

33 MHz: 1993.
40 MHz: 1993.
50 MHz.

Technology: CMOS.
1.1E6 transistors.
Die size: 196 mm2.

Cyrix M6 CPU.

ID: DH = 0x00 (family ID), DL = 0x06 (model ID).

DIR0 register: 0x1A.


2.36.9 Cyrix FasCache Cx486DX-V33 CPU

Low voltage (3.3 V) version of the Cyrix FasCache Cx486DX CPU.

September 1993.

25 MHz.
33 MHz.

Technology: CMOS.

ID: DH = 0x00 (family ID), DL = 0x06 (model ID).

DIR0 register: 0x1A.


2.36.10 Cyrix FasCache Cx486DX2 CPU

Clock doubled Cyrix FasCache Cx486DX CPU.

September 1993.

20/40 MHz.
25/50 MHz.
33/66 MHz.
40/80 MHz.

Technology: CMOS.

Cyrix M7 CPU.

ID: DH = 0x00 (family ID), DL = 0x07 (model ID).

DIR0 register: 0x1B.


2.36.11 Cyrix FasCache Cx486DX2-V33 CPU

Low voltage (3.3V) version of the Cyrix FasCache Cx486DX2 CPU.

33/66 MHz.
40/80 MHz.

Technology: CMOS.

ID: DH = 0x00 (family ID), DL = 0x07 (model ID).

DIR0 register: 0x1B.


2.36.12 Cyrix FasCache Cx486DX2-V CPU

Low voltage (4 V) version of the Cyrix FasCache Cx486DX2 CPU.

8 kbyte cache: write-back.

33/66 MHz (announced: fourth quarter 1994).
40/80 MHz (announced: fourth quarter 1994).

Technology: IBM 0.65 micron CMOS.

ID: DH = 0x04 (family ID), DL = 0x80 (model ID, revision).

DIR0 register: 0x1B.


2.36.13 Cyrix FasCache Cx486DX4 CPU

Clock tripled Cyrix FasCache Cx486DX CPU.
Intel i80486DX4 P24C CPU pin compatible.
3 V core, 5 V tolerant I/O.

Dual SMM support: Cyrix SMM / SL compatible SMM.

8 kbyte cache: write-back.

Cyrix FasCache Cx486DX4-GP CPU:
core/bus speed ratio: 3,
DIR0 register: 0x1F,
package: Cyrix FasCache Cx486DX2 CPU pin compatible:
168 pin PGA (Pin Grid Array),
208 pin QFP (Quad Flat Package).
Cyrix FasCache Cx486DX4-GP4 CPU and Cyrix FasCache Cx486DX4-QP:
pin selectable core/bus speed ratio,
not Cyrix FasCache Cx486DX2 CPU pin compatible,
DIR0 register: 0x1B (CLOCKMUL = 0), 0x1F (CLOCKMUL = 1).

25/75 MHz.
33/100 MHz.

September 1995.

Technology: CMOS.

Cyrix M9 CPU.


2.36.14 Cyrix 5x86 CPU

Cyrix 586 CPU with Intel i80486DX4 P24D CPU bus interface.
64 bit internal data bus, 32 bit external data bus.
Clock: 2x, 3x.

16 kbyte unified cache: write-back/write-through, 4-way set-associative,
4 sets of 256 lines, 16 bytes per line.

Superpipelined superscalar: data forwarding, branch prediction,
BTB (Branch Target Buffer),
decoupled load/store unit.
MMU (Memory Management Unit): 32-entry TLB (Translation Look-aside buffer).

SMM (System Management Mode): stop-clock, FPU auto-idle, hardware suspend,
static core.

33/100 or 50/100 MHz: 3.5 W.
40/120 MHz.

3.45 V core, 5 V tolerant I/O.

Package: 168 pin PGA (Pin Grid Array),
208 pin QFP (Quad Flat Package).

Technology: 0.65 micron CMOS (IBM).
2.0E6 transistors.
Die size: 144 mm2.

Cyrix M1sc CPU.


2.37 Texas Instruments TI486 CPU

2.37.1 Texas Instruments TI486SXL-GA CPU (Potomac)

Intel i80486SX CPU instruction/pin compatible.

8 kbyte cache: write-through, 2-way set-associative, 1024 sets,
4 bytes per line.

40 MHz: february 1994.

Package: ceramic PGA (Pin Grid Array).

Technology: CMOS.

ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.


2.37.2 Texas Instruments TI486SXL-V-GA CPU (Potomac)

Low power (3.3 V) version of the Texas Instruments TI486SXL-GA CPU.

33 MHz: february 1994.

Technology: CMOS.

ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.


2.37.3 Texas Instruments TI486SXL2-GA CPU (Potomac)

Clock doubled version of the Texas Instruments TI486SXL-GA CPU.

20/40 MHz: february 1994.
25/50 MHz: february 1994.

Technology: CMOS.

ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.


2.37.4 Texas Instruments TI486SXL2-V-GA CPU (Potomac)

Clock doubled, low power (3.3 V) version of the
Texas Instruments TI486SXL-GA CPU.

20/40 MHz: february 1994.

Technology: CMOS.

ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.


2.37.5 Texas Instruments TI486DX2 CPU

Cyrix core.
Intel and Cyrix pin compatible.

33/66 MHz.
40/80 MHz.


2.37.6 Texas Instruments TI486DX4 CPU

Cyrix FasCache Cx486DX4 CPU with Texas Instruments TI486DX2 CPU pin layout.

33/100 MHz (announced December 1995).


2.38 SGS-Thomson ST486 CPU

2.38.1 SGS-Thomson ST486DX2 CPU

Cyrix FasCache Cx486DX2 CPU.

33/66 MHz.


2.39 UMC 486 CPU

The UMC 486 CPU does violate some of Intel's patents and will therefore not be
sold in the USA.

SMM (System Management Mode).

CPUID: "UMC UMC UMC".

Some 3.3 V U5 CPUs are sold as 3 V parts.


2.39.1 UMC U5S CPU

Intel i80486SX CPU instruction/pin compatible, no FPU (Floating Point Unit).

8 kbyte cache.
4 deep write buffer.

25 MHz: August 1994.
33 MHz: 2.25 W, August 1994.
40 MHz: August 1994.

Manufacturing: 0.6 micron CMOS.

ID: step level A: DH = 0x04 (family ID), DL = 0x23 (model ID, revision).

CPUID: family = 0x4, model = 0x2.


2.39.2 UMC U5SD CPU

Intel i80486DX CPU pin compatible UMC U5S CPU.

25 MHz: August 1994.
33 MHz: 2.25 W, August 1994.
40 MHz: August 1994.

Manufacturing: 0.6 micron CMOS.

ID: DH = 0x04 (family ID), DL = 0x1X (model ID, revision).

CPUID: family = 0x4, model = 0x1.


2.39.3 UMC U5SF CPU

UMC U5S CPU with 208 pin QFP (Quad Flat Package) package.

33 MHz (UMC U5SF-SUPER33 CPU).


2.39.4 UMC U5SLV CPU

3.3 V version of the UMC U5S CPU.

25 MHz (UMC U5SLV-SUPER25 CPU).
33 MHz (UMC U5SLV-SUPER33 CPU): 0.76 W, August 1994.

Manufacturing: 0.6 micron CMOS.

Package: 196 pin PGA (Pin Grid Array).


2.39.5 UMC U5FLV CPU

UMC U5SLV CPU with 208 pin LQFP package.

25 MHz (UMC U5FLV-SUPER25 CPU).
33 MHz (UMC U5FLV-SUPER33 CPU).


Label: UMC U5SDLV:
D: 486DX pin compatible PGA (Pin Grid Array),
_: 486SX pin compatible PGA (Pin Grid Array),
F: 486SX pin compatible LQFP,
LV: 3.3 V,
_: 5 V.


2.39.6 UMC U486DX2 CPU

CPUID: 0x43x.


2.39.7 UMC U486SX2 CPU

CPUID: 0x45x.


2.40 Intel OverDrive CPU for Intel i80486 CPU

Many 486 CPU motherboards contain an Intel OverDrive socket in which a more
powerful CPU can be placed (ODP: OverDrive Processor), this being an
Intel i80486DX2 CPU, an Intel i80486DX4 CPU, or an Intel Pentium CPU. It is
possible to remove the old CPU while upgrading. All output pins of the
original CPU are put in 3-state and the power consumption is reduced when the
UP# pin (Upgrade Present) is activated.

An Intel OverDrive CPU will be made available that will fit in the original
PGA (Pin Grid Array) (ODPR: OverDrive Processor Replacement), so motherboards
without an Intel OverDrive socket can be upgraded too.

At this moment it is still unsure if all motherboards with an
Intel OverDrive socket can indeed be upgraded to an Intel Pentium CPU. The
Intel Pentium P24T CPU (ODP), the Intel Pentium CPU upgrade for the blue
238 pin PGA OverDrive socket (Socket 2: 5 V), appears to produce too much heat
for most thermally not compliant systems. It is not even sure if there will
ever be an Intel Pentium CPU upgrade for those motherboards at all (see Intel
OverDrive Processor Upgradability Guide). For the newer motherboards with a
white 237 pin PGA OverDrive socket (Socket 3: 3.3 V, 5 V), that do satisfy the
heat specifications, there will be an Intel Pentium CPU at 3.3 V with a
ventilator on the IC. There are also black 168 pin OverDrive sockets (standard
486 socket) around; these can contain an Intel i80486DX2 ODP CPU or an
Intel i80486DX4 ODP CPU. For the black 169 pin OverDrive sockets (Socket 1:
5 V) of 486SX systems, an Intel i80487SX CPU, an Intel i80486DX2 ODP CPU, or
an Intel i80486DX4 ODP CPU is available. For the 235 pin Overdrive socket
(Socket 6: 3 V) of 486DX4 systems, the same Intel Pentium CPU at 3.3 V that
could be used with Socket 3, can be used here as well.


2.40.1 Intel i80486DX2 CPU for Intel i80486DX CPU (ODPR)

20/40 MHz.
25/50 MHz.
33/66 MHz.

SL Enhanced from June 1993.

No longer available from April 1996.

Package: 168 pin PGA (Pin Grid Array).

Technology: CMOS.

ID: step level A0-A2: DH = 0x04 (family ID), DL = 0x32 (model ID, revision),
step level B1: DH = 0x04 (family ID), DL = 0x33 (model ID, revision),
step level aA0, aA1 (SL Enhanced): DH = 0x04 (family ID), DL = 0x34
(model ID, revision),
step level aB0, aC0 (SL Enhanced): DH = 0x04 (family ID), DL = 0x35
(model ID, revision),
step level A (write-back): DH = 0x04 (family ID), DL = 0x7X (model ID,
revision).

P4T


2.40.2 Intel i80486DX2 CPU for Intel i80486SX CPU (ODPR)

20/40 MHz.
25/50 MHz.
33/66 MHz.

SL Enhanced from June 1993.

No longer available from April 1996.

Package: 168 pin PGA (Pin Grid Array).

Technology: CMOS.

ID: step level A0-A2: DH = 0x04 (family ID), DL = 0x32 (model ID, revision),
step level B1: DH = 0x04 (family ID), DL = 0x33 (model ID, revision),
step level aA0, aA1 (SL Enhanced): DH = 0x04 (family ID), DL = 0x34
(model ID, revision),
step level aB0, aC0 (SL Enhanced): DH = 0x04 (family ID), DL = 0x35
(model ID, revision),
step level A (write-back): DH = 0x04 (family ID), DL = 0x7X (model ID,
revision).

P4T


2.40.3 Intel i80486DX2 CPU for Intel i80486DX CPU (ODP)

16/32 MHz.
20/40 MHz.
25/50 MHz.
33/66 MHz.

SL Enhanced from June 1993.

No longer available from April 1996.

Package: 168 pin PGA (Pin Grid Array).

Technology: CMOS.

ID: step level A0-A2: DH = 0x04 (family ID), DL = 0x32 (model ID, revision),
step level B1: DH = 0x04 (family ID), DL = 0x33 (model ID, revision),
step level aA0, aA1 (SL Enhanced): DH = 0x04 (family ID), DL = 0x34
(model ID, revision),
step level aB0, aC0 (SL Enhanced): DH = 0x04 (family ID), DL = 0x35
(model ID, revision),
step level A (write-back): DH = 0x04 (family ID), DL = 0x7X (model ID,
revision).


2.40.4 Intel i80486DX2 CPU for Intel i80486SX CPU (ODP)

16/32 MHz.
20/40 MHz.
25/50 MHz.
33/66 MHz.

SL Enhanced from June 1993.

No longer available from April 1996.

Package: 169 pin PGA (Pin Grid Array) (487SX).

Technology: CMOS.

P23T.

ID: step level A0-A2: DH = 0x04 (family ID), DL = 0x32 (model ID, revision),
step level B1: DH = 0x04 (family ID), DL = 0x33 (model ID, revision),
step level aA0, aA1 (SL Enhanced): DH = 0x04 (family ID), DL = 0x34
(model ID, revision),
step level aB0, aC0 (SL Enhanced): DH = 0x04 (family ID), DL = 0x35
(model ID, revision),
step level A (write-back): DH = 0x04 (family ID), DL = 0x7X (model ID,
revision).


2.40.5 Intel i80486DX4 CPU for Intel i80486DX CPU, Intel i80486DX2 CPU
(ODP)

3.3 V core (voltage regulator), 5 V I/O.

25/75 MHz max (DX4ODPR75): October 1994, iCOMP 319.
33/100 MHz max (DX4ODPR100): October 1994, iCOMP 435.

No longer available from fall 1996.

Package: 169 pin PGA (Pin Grid Array) (487SX).

ID: step level A: DH = 0x14 (family ID), DL = 0x80 (model ID, revision).


2.40.6 Intel Pentium P24T CPU (ODP)

25 MHz: December 1994.
33 MHz: December 1994.

5 V.

ID: DH = 0x15 (model ID, family ID), DL = 0x31 (revision).


2.40.7 Intel Pentium P24CT CPU (ODP)

32 kbyte cache: 16 kbyte code, 16 kbyte data.

25/63 MHz (PODP5V63): for 25 MHz external bus systems, January 1994,
235 pin PGA (Pin Grid Array), iCOMP 443.
33/83 MHz (PODP5V83): for 33 MHz external bus systems, October 1995,
237/238 pin PGA (Pin Grid Array), iCOMP 581,
no longer available from March 1998.

ID: DH = 0x15 (model ID, family ID), DL = 0x2X (revision).

CPUID: step level B1 (25/63 MHz, SZ953): 1531,
step level B2 (25/63 MHz, SZ990): 1531,
step level C0 (33/83 MHz, SU014): 1532.


2.41 Cyrix Overdrive CPU

DIR0 register: 0xFD.

Aad Offerman

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Jul 27, 1998, 3:00:00 AM7/27/98
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Archive-name: pc-hardware-faq/chiplist/part2
Last-modified: 1998/06/23
Version: 9.9.5


2 CPU (Central Processing Unit)

2.1 Introduction

The central processing unit (CPU) is the "brain" of the computer. Its function
is to execute programs stored in the main memory by fetching their
instructions, examining them, and then executing them one after another.


2.2 Intel i4004 CPU

4 bit data bus.
12 bit address bus (multiplexed).
Separate address space for instructions and data.

1970.

Package: 16 pin ceramic DIP (Dual In-line Package).

Technology: PMOS.
Die size: 24 mm2.
2250 transistors.

First microprocessor ever build.


2.3 Intel i4040 CPU

Intel i4004 CPU with extra features: more instructions,
interrupt support.

4 bit data bus.
12 bit address bus (multiplexed).
Separate address space for instructions and data.

1972.

Package: 24 pin ceramic DIP (Dual In-line Package).

Technology: PMOS.


2.4 Intel i8008 CPU

8 bit data bus.
14 bit address bus (multiplexed).

300 kHz.

April 1972.

Package: 18 pin ceramic DIP (Dual In-line Package).

Technology: PMOS.
3300 transistors.


2.5 Intel i8080/i8080A CPU

Intel i8008 CPU with stack.

8 bit data bus.
16 bit address bus.

Intel i8080 CPU: 2 MHz, PMOS.
Intel i8080A-2 CPU: 2.67 MHz, NMOS.
Intel i8080A-1 CPU: 3.125 MHz, NMOS.
Intel iM8080A: military (-55 - 125 C).

April 1974.

Package: 40 pin CERDIP (CERamic Dual In-line Package).

Intel i8080 CPU: 1973, PMOS, 4500 transistors.
Intel i8080A CPU: 1976, NMOS, 4000 transistors.


2.6 Zilog Z80 CPU

Intel i8080 CPU upward instruction compatible.

Not Intel i8080 CPU pin compatible.

2.5 MHz: NMOS.
4 MHz: NMOS.
6 MHz: NMOS.
8 MHz: NMOS.
10 MHz: CMOS.

1976.

Package: 40 pin CERDIP (CERamic Dual In-line Package).


2.7 Intel i8085A/i8085AH CPU

Intel i8080 CPU upward instruction compatible.
Extra instructions: SIM (Set Interrupt Mask),
RIM (Read Interrupt Mask).
Extra interrupt lines, including NMI (Non-Maskable Interrupt).

8 bit data bus.
16 bit address bus.
Data and address bus are multiplexed.

1976.

Intel i8085A CPU: 3 MHz, NMOS.
Intel iM8085A CPU: military (-55 - 125 C), NMOS.
Intel i8085AH-2 CPU: 5 MHz, HMOS.
Intel i8085AH-1 CPU: 6 MHz, HMOS.
Intel iM8085AH CPU: military (-55 - 125 C), HMOS.

Package: 40 pin CERDIP (CERamic Dual In-line Package).

6200 transistors.


2.8 Intel i8086A/i80C86A CPU, Intel i8088A/i80C88A CPU

1 Mbyte address space, 64 kbyte per segment.

Technology: 2.0 micron.
29E3 transistors.


2.8.1 Intel i8086A/i80C86A CPU

16 bit internal data bus.
16 bit external data bus.
20 bit address bus.
Data and address bus are multiplexed.

May 1978.

Intel i8086A CPU: 4 MHz, NMOS.
Intel i8086AH CPU: 5 MHz, HMOS.
Intel i8086AH-2 CPU: 8 MHz, HMOS.
Intel i8086AH-1 CPU: 10 MHz, HMOS.
Intel i80C86A CPU: 5 MHz, CMOS.
Intel i80C86A-2 CPU: 8 MHz, CMOS.
Intel i80C86A-1 CPU: 10 MHz, CMOS.
12 Mhz: CMOS.
Intel iM80C86A CPU: military (-55 - 125 C).

Used in IBM PC clones, IBM PC/XT clones.

Package: 40 pin CERDIP (CERamic Dual In-line Package).


2.8.2 Intel i8088A/i80C88A CPU

16 bit internal data bus.
8 bit external data bus (can co-operate with all Intel i8085 CPU
periphery chips).
20 bit address bus.
Data and address bus are multiplexed.

February 1979.

Intel i80C88A CPU: 5 MHz, CMOS.
Intel i80C88A-2 CPU: 8 MHz, CMOS.
Intel i80C88A-1 CPU: 10 MHz, CMOS.
12 MHz: CMOS.

Package: 40 pin CERDIP (CERamic Dual In-line Package).

Used in IBM PC (Personal Computer), IBM PC/XT (eXtended Technology).


2.9 AMD Am8086/Am80C86 CPU, AMD Am8088/Am80C88 CPU

2.9.1 AMD Am8086/Am80C86 CPU

Intel i8086 CPU instruction/pin compatible.

AMD Am8086-1 CPU: 10 MHz, HMOS.
AMD Am80C86 CPU: 5 MHz, CMOS.
AMD Am80C86-2 CPU: 8 MHz, CMOS.
AMD Am80C86-1 CPU: 10 MHz, CMOS.


2.9.2 AMD Am8088/Am80C88 CPU

Intel i8088 CPU instruction/pin compatible.

AMD Am8088 CPU: 5 MHz, HMOS.
AMD Am8088-2 CPU: 8 MHz, HMOS.
AMD Am8088-1 CPU: 10 MHz, HMOS.


2.10 Harris HS80C86/883 CPU, Harris HS80C88/883 CPU

2.10.1 Harris HS80C86/883 CPU

Intel i8086 CPU instruction/pin compatible.

Harris HS80C86/883 CPU: 5 MHz, CMOS.
Harris HS80C86-2/883 CPU: 8 MHz, CMOS.
Harris HS80C86-1/883 CPU: 10 MHz, CMOS.
Harris HSMD80C86 CPU: military (-55 - 125 C), CMOS.


2.10.2 Harris HS80C88/883 CPU

Intel i8088 CPU instruction/pin compatible.

Harris HS80C88/883 CPU: 5 MHz, CMOS.
Harris HS80C88-2/883 CPU: 8 MHz, CMOS.
Harris HS80C88-1/883 CPU: 10 MHz, CMOS.


2.11 Siemens SAB8086 CPU, Siemens SAB8088 CPU

2.11.1 Siemens SAB8086 CPU

Intel i8086 CPU instruction/pin compatible.

Siemens SAB8086-2P CPU: 8 MHz.
Siemens SAB8086-1P CPU: 10 MHz.


2.11.2 Siemens SAB8088 CPU

Intel i8088 CPU instruction/pin compatible.

Siemens SAB8088-I-P CPU: 16 MHz.

1986.


2.12 Hitachi H80C88 CPU

Intel i8088 CPU instruction/pin compatible.

1982.

Technology: CMOS.


2.13 Contemporary CPUs

Contemporary 16 bit CPUs to 8086/8088 were Zilog Z8000 CPU,
Fairchild 9445 CPU, Texas Instruments TI9900 CPU and Mil-Std 1750A CPU.
Last is reason DOD (Department Of Defence) contractors were not interested in
8086/8088. Mil-Std 1750A CPU was specified in all contracts of 1979 - 1984
period.
Texas Instruments TI9900 CPU was probably the best of the lot, but
Texas Instruments considered it a closed architecture, so no-one used it.


2.14 Intel i80186/i80C186 CPU, Intel i80188/i80C188 CPU

Intel i8086 CPU / Intel i8088 CPU with extra features:
2 programmable DMA controllers (Direct Memory Access),
3 timers,
PIC (Programmable Interrupt Controller),
integrated clock generator,
Intel i80C186 CPU, Intel i80C188 CPU: DRAM refresh control unit,
Intel i80C186 CPU, Intel i80C188 CPU: power save mode,
extra instructions: all of the Intel i80286 CPU real mode instructions.
The Intel i80C188 CPU has no NPX interface.


2.14.1 Intel i80186/i80C186 CPU

16 bit internal data bus.
16 bit external data bus.
20 bit address bus.

1983.

Intel i80186 CPU: 6 MHz, NMOS.
Intel i80186 CPU: 8 MHz, NMOS.
Intel i80186 CPU: 10 MHz, NMOS.
Intel i80C186 CPU: 10 MHz, CMOS.
Intel i80C186-12 CPU: 12.5 MHz, CMOS.
Intel i80C186-16 CPU: 16 MHz, CMOS.
Intel iM80C186 CPU: military (-55 - 125 C), 10 MHz, CMOS.
Intel iM80C186-12 CPU: military (-55 - 125 C), 12.5 MHz, CMOS.

Intel i80C186XL CPU: low power, static core version of the Intel i80C186 CPU:
Intel i80C186XL CPU: 10 MHz, CMOS,
Intel i80C186XL12 CPU: 12.5 MHz, CMOS,
Intel i80C186XL16 CPU: 16 MHz, CMOS,
Intel i80C186XL20 CPU: 20 MHz, CMOS.

Intel i80C186EA CPU: Intel i80C186 CPU with extra features: idle mode,
power down mode:
Intel i80L186EA8 CPU: 3 V, 8 MHz, CMOS,
Intel i80C186EA12 CPU: 12.5 MHz, CMOS,
Intel i80C186EA16 CPU: 16 MHz, CMOS,
Intel i80C186EA20 CPU: 20 MHz, CMOS.

Intel i80C186EB CPU: low power, static core Intel i80C186 CPU with 2 serial
channels, instead of DMA:
Intel i80C186EB-8 CPU: 8 MHz, CMOS,
Intel i80L186EB-8 CPU: 3 V, 8 MHz, CMOS,
Intel i80C186EB-13 CPU: 13 MHz, CMOS,
Intel i80C186EB-16 CPU: 16 MHz, CMOS.

Intel i80C186EC CPU: Intel i80C186 CPU with extra features: low power,
static core, 2 serial channels, 4 DMA channels, 32 bit watchdog timer:
Intel i80C186EC-13 CPU: 13 MHz, CMOS,
Intel i80C186EC-16 CPU: 16 MHz, CMOS.


2.14.2 Intel i80188/i80C188 CPU

16 bit internal data bus.
8 bit external data bus (can co-operate with all Intel i8085 CPU
periphery chips).
20 bit address bus.

1983.

Intel i80188 CPU: 6 MHz, NMOS.
Intel i80188 CPU: 8 MHz, NMOS.
Intel i80C188 CPU: 10 MHz, CMOS.
Intel i80C188-12 CPU: 12.5 MHz, CMOS.
Intel i80C188-16 CPU: 16 MHz, CMOS.

Intel i80C188XL CPU: low power, static core version of the Intel i80C188 CPU:
Intel i80C188XL CPU: 10 MHz, CMOS,
Intel i80C188XL12 CPU: 12 MHz, CMOS,
Intel i80C188XL16 CPU: 16 MHz, CMOS,
Intel i80C188XL20 CPU: 20 MHz, CMOS.

Intel i80C188EA CPU: Intel i80C188 CPU with extra features: idle mode,
power down mode:
Intel i80L188EA8 CPU: 3 V, 8 MHz, CMOS,
Intel i80C188EA12 CPU: 12.5 MHz, CMOS,
Intel i80C188EA16 CPU: 16 MHz, CMOS,
Intel i80C188EA20 CPU: 20 MHz, CMOS.

Intel i80C188EB CPU: low power, static core Intel i80C188 CPU with 2 serial
channels instead of DMA:
Intel i80C188EB-8 CPU: 8 MHz, CMOS,
Intel i80L188EB-8 CPU: 3 V, 8 MHz, CMOS,
Intel i80C188EB-13 CPU: 13 MHz, CMOS,
Intel i80C188EB-16 CPU: 16 MHz, CMOS.

Intel i80C188EC CPU: Intel i80C188 CPU with extra features: low power,
static core, 2 serial channels, 4 DMA channels, 32 bit watchdog timer:
Intel i80C188EC-13 CPU: 13 MHz, CMOS,
Intel i80C188EC-16 CPU: 16 MHz, CMOS.


2.15 AMD Am80186/Am80188 CPU

Intel i80186/i80188 CPU upward instruction compatible.


2.15.1 AMD Am80L186 CPU

Intel i80186 CPU bus interface.

16 MHz: 3.3 V, 1995.

AMD Embedded Processors E86 Family.


2.15.2 AMD Am80L188 CPU

Intel i80188 CPU bus interface.

16 MHz: 3.3 V, 1995.

AMD Embedded Processors E86 Family.


2.15.3 AMD Am186EM CPU

Intel i80286 CPU style bus interface.
Extra Features: 2 DMA channels,
watchdog timer,
asynchronous & synchronous serial ports,
32 programmable I/O pins.

25 MHz: 1995.
33 MHz: 1995.

40 MHz: 1995.

Package: PQT100.

AMD Embedded Processors E86 Family.


2.16 NEC V30/V20 CPU

Intel i80186 CPU / Intel i80188 CPU upward instruction compatible.
No protected mode.
Extra features: extra instructions: BCD,
Intel i8080 CPU simulation,
fewer CPI (Cycles Per Instruction).


2.16.1 NEC V30 CPU

Intel i8086 CPU pin compatible.

10 MHz.

mPD70116.

NEC V30H CPU: 10, 12, 16 MHz,
packages: 40 pin DIP (Dual In-line Package),
44 pin PLCC (Plastic Leaded Chip Carrier),
52 pin PFP (QFP (Quad Flat Package)),
mPD70116H.
NEC V35 CPU: extra instructions for register bank switches and task switches,
packages: 84 pin PLCC (Plastic Leaded Chip Carrier),
94 pin QFP (Quad Flat Package),
mPD70330, mPD70332.
NEC V35 Plus CPU: NEC V35 CPU with integrated peripherals: PIC, DMA, ports,
serial, timer,
256 bytes RAM,
8 kbyte ROM,
mPD70335.
NEC V35 Software Guard CPU: NEC V35 CPU with 8086 emulation mode and security
mode,
mPD70337.
NEC V50 CPU: undefined opcode triggers INT6,
same speeds,
packages: 68 pin PGA (Pin Grid Array),
68 pin PLCC (Plastic Leaded Chip Carrier),
80 pin PFP (QFP (Quad Flat Package)),
mPD70216.
NEC V50H CPU: 10, 12, 16 MHz,
packages: 68 pin PGA (Pin Grid Array),
80 pin PFP (QFP (Quad Flat Package)),
mPD70216H.
NEC V55 CPU: NEC V50 CPU,
speeds up to 16 MHz.


2.16.2 NEC V20 CPU

Intel i8088 CPU pin compatible.

8 MHz.
10 MHz.

mPD70108.

Also made by Sony under license from NEC.

NEC V20H CPU: 10, 12, 16 MHz,
packages: 40 pin DIP (Dual In-line Package),
44 pin PLCC (Plastic Leaded Chip Carrier),
52 pin PFP (QFP (Quad Flat Package)),
mPD70108H.
NEC V25 CPU: extra instructions for register bank switches and task switches,
packages: 84 pin PLCC (Plastic Leaded Chip Carrier),
94 pin QFP (Quad Flat Package),
mPD70320, mPD70322.
NEC V25 Plus CPU: NEC V25 CPU with integrated peripherals: PIC, DMA, ports,
serial, timer,
256 bytes RAM,
8 kbyte ROM,
mPD70325.
NEC V25 Software Guard CPU: NEC V25 CPU with 8086 emulation mode and security
mode,
mPD70327.
NEC V40 CPU: undefined opcode triggers INT6,
same speeds,
packages: 68 pin PGA (Pin Grid Array),
68 pin PLCC (Plastic Leaded Chip Carrier),
80 pin PFP (QFP (Quad Flat Package)),
mPD70208.
NEC V40H CPU: 10, 12, 16 MHz,
packages: 68 pin PGA (Pin Grid Array),
80 pin PFP (QFP (Quad Flat Package)),
mPD70208H.
NEC V45 CPU: NEC V40 CPU,
speeds up to 16 MHz.


2.17 Siemens SAB80186 CPU, Siemens SAB80188 CPU

2.17.1 Siemens SAB80186 CPU

Intel i80186 CPU instruction/pin compatible.

Siemens SAB80186-N CPU: 8 MHz.
Siemens SAB80186-1 CPU: 10 MHz.
Siemens SAB80186-16 CPU: 16 MHz.


2.17.2 Siemens SAB80188 CPU

Intel i80188 CPU instruction/pin compatible.

Siemens SAB80188-N CPU: 8 MHz.
Siemens SAB80188-1N CPU: 10 MHz.


2.18 Intel i80886 CPU


2.19 Intel i80286 CPU

Real mode: Intel i8086/i8088 CPU mode.
Protected mode: 16 MByte address space, 64 kbyte per segment,
1 Gbyte virtual memory.

16 bit data bus.
24 bit address bus.

1982.

6 MHz.
8 MHz: PLCC (Plastic Leaded Chip Carrier).
10 MHz: PLCC (Plastic Leaded Chip Carrier).
12 MHz: PLCC (Plastic Leaded Chip Carrier).
16 MHz: PLCC (Plastic Leaded Chip Carrier).
20 MHz.

Package: 68 pin CERDIP (CERamic Dual In-line Package).

Technology: HMOS.
134E3 transistors.

Used in IBM PC/AT (Advanced Technology).


2.20 AMD Am80286/Am80C286 CPU

Intel i80286 CPU instruction/pin compatible.

AMD Am80286 CPU: 8 MHz, HMOS.
AMD Am80286 CPU: 10 MHz, HMOS.
AMD Am80286 CPU: 12 MHz, HMOS.
AMD Am80286 CPU: 16 MHz, HMOS.
AMD Am80C286 CPU: 10 MHz, CMOS.
AMD Am80C286 CPU: 12 MHz, CMOS.
AMD Am80C286 CPU: 16 MHz, CMOS.
AMD Am80C286 CPU: 20 MHz, CMOS.
AMD Am80EC286 CPU: low power version of the AMD Am80C286 CPU.


2.21 Harris 80C286 CPU

Intel i80286 CPU instruction/pin compatible.

10 MHz.
12.5 MHz.
16 MHz.
20 MHz.
25 MHz.

Technology: CMOS.


2.22 Siemens SAB80286 CPU

Intel i80286 CPU instruction/pin compatible.

Siemens SAB80286 CPU: 8 MHz.
Siemens SAB80286-1-N CPU: 10 MHz.
Siemens SAB80286-12-N CPU: 12 MHz.
Siemens SAB80286-16 CPU: 16 MHz.

2.23 Fujitsu 80286 CPU


2.24 Kruger 80286 CPU


2.25 Intel i80386 CPU

Real mode: Intel i8086/i8088 CPU mode.
Protected mode: 64 Tbyte virtual memory, 4 Gbyte per segment.
Virtual 8086 mode (V86 mode): parallel simulation of more virtual
Intel i8086/i8088 CPUs.

POPAD bug: EAX register is trashed when there is a memory access instruction
directly after the POPAD instruction.


2.25.1 Intel i80386/i80386DX CPU

32 bit internal data bus.

32 bit external data bus (DX: Double-word eXternal).
32 bit address bus.

12 MHz: first 16 MHz CPUs had clock speed troubles and were released as
12 MHz items.
16 MHz: early Intel i80386 CPUs had a bug in the 32 bit MUL instruction (MUL
bug); it is fixed in the double-sigma step level,
no longer available.
20 MHz: no longer available.
25 MHz: iCOMP 49.
33 MHz: 2000 mW, iCOMP 68.

October 1985.

Package: 132 pin PGA (Pin Grid Array).

Technology: 0.8 micron CMOS.
275E3 transistors.

ID: AH = 0x03 (Intel i80386 CPU).

ID: step level A (Intel i80386 CPU): DH = 0x00 (model ID, family ID),
step level B0-B10 (Intel i80386 CPU, CMOS III): DH = 0x03 (model ID,
family ID), DL = 0x03 (revision),
step level D0 (Intel i80386DX CPU, CMOS III): DH = 0x03 (model ID,
family ID), DL = 0x05 (revision),
step level D1-D2 (Intel i80386DX CPU, CMOS IV): DH = 0x03 (model ID,
family ID), DL = 0x08 (revision),
step level Ex, Fx: DH = 0x03 (model ID, family ID), DL = 0x08 (revision).


2.25.2 Intel i80386SX CPU

32 bit internal data bus.

16 bit external data bus (SX: Single-word eXternal).
24 bit address bus.

June 1988.

16 MHz.
20 MHz: iCOMP 32.
25 MHz: iCOMP 39.
33 MHz.

Package: 100 pin QFP (Quad Flat Package).

Technology: 0.8 micron CMOS.

ID: step level A0: DH = 0x23 (model ID, family ID), DL = 0x04 (revision),
step level B: DH = 0x23 (model ID, family ID), DL = 0x05 (revision),
step level C, D, E: DH = 0x23 (model ID, family ID), DL = 0x08 (revision).


2.25.3 Intel i80386SL CPU

Low power version of the Intel i80386SX CPU: SMM (System Management Mode).
Static core.
Extra pins assigned for power management.

Extra features: PI-bus (Peripheral Interface),
cache controller, tag RAM,
MCU (Memory Control Unit),
ISA-bus driver (Industry Standard Architecture).

Intel i80386SX CPU upward pin compatible.
Other package: 196 pin surface mounted QFP (Quad Flat Package)
(KC80386SLB1A, ISA SX621).

October 1990.

16 MHz.
20 MHz.
25 MHz, iCOMP 41.
33 MHz.

Technology: CMOS.

ID: step level A0: DH = 0x43 (model ID, family ID), DL = 0x10 (revision),
step level A1: DH = 0x43 (model ID, family ID), DL = 0x10 (revision),
step level A2: DH = 0x43 (model ID, family ID), DL = 0x10 (revision),
step level A3: DH = 0x43 (model ID, family ID), DL = 0x10 (revision),
step level B0: DH = 0x43 (model ID, family ID), DL = 0x11 (revision),
step level B1: DH = 0x43 (model ID, family ID), DL = 0x11 (revision).

Signature register (0x30E, OMCU): step level A0: 0x4300,
step level A1: 0x4300,
step level A2: 0x4301,
step level A3: 0x4302,
step level B0: 0x4310,
step level B1: 0x4311.


2.25.4 Intel RapidCAD CPU

Intel i80386 CPU with FPU (Floating Point Unit) (same implementation as
Intel i80486DX CPU).

The Intel RapidCAD CPU consists of a set of 2 chips. The Intel RapidCAD-1
(132 pin PGA) contains the Intel i80386 CPU with FPU. The Intel RapidCAD-2
(68 pin PGA) fits in the Intel i80387DX NPX socket and contains a PLA for the
FERR signal generation.

Intel i80386DX CPU / Intel i80387DX NPX pin compatible.

1992.

25 MHz.
33 MHz: 2.6 W typical, 3500 mW max.

800.000 transistors.
Technology: 0.8 micron CHMOS IV.

ID: step level A: DH = 0x03 (family ID), DL = 0x40 (model ID, revision),
step level B: DH = 0x03 (family ID), DL = 0x41 (model ID, revision).


2.25.5 Intel i80376 microprocessor

Embedded version of Intel i80386SX CPU.
Intel i80386SX CPU pin compatible.

Intel i80386 CPU instruction set, 32 bit protected mode only, no real mode, no
V86 mode, no 286 mode.
No MMU (Memory Management Unit).

16 MHz.
20 MHz.

1988.

Package: 100 pin QFP (Quad Flat Package),
88 pin PGA (Pin Grid Array).

ID: step level A0: DH = 0x33 (model ID, family ID), DL = 0x05 (revision),
step level B: DH = 0x33 (model ID, family ID), DL = 0x08 (revision).


2.25.6 Intel i386SX microprocessor

Embedded version of Intel i80386SX CPU.
Static core.

24 bit address bus.

16 MHz: 5 V, 0-16 MHz, 1993.
20 MHz: 5 V, 0-20 MHz, 1993.
25 MHz: 5 V, 0-25 MHz, 1993.

Package: 100 pin PQFP (Plastic Quad Flat Package),
die,
military (-55 - 125 C).

Technology: CMOS.

ID: DH = 0x23 (model ID, family ID), DL = 0x09 (revision).


2.25.7 Intel i386CX microprocessor

Embedded version of Intel i80386SX CPU.
Static core.

SMM (System Management Mode): system & power management: idle mode, powerdown,
powersave.

26 bit address bus.

12 MHz: 3 V, 0-12 MHz, 1993.
20 MHz: 3.3 V, 0-20 MHz, 1993.
25 MHz: 5 V, 0-25 MHz, 1993.

Package: 100 pin PQFP (Plastic Quad Flat Package),
100 pin SQFP (Shrink Quad Flat Package),
die,
military (-55 - 125 C).

Technology: CMOS.

ID: step level A: DH = 0x23 (model ID, family ID), DL = 0x09 (revision).


2.25.8 Intel i386EX microprocessor

Embedded version of Intel i80386SX CPU.
Static core.

SMM (System Management Mode): system & power management: idle mode, powerdown,
powersave.

26 bit address bus.

16 MHz: 3 V, 0-16 MHz, 1994.
20 MHz: 3.3 V, 0-20 MHz, 1994.
25 MHz: 5 V, 0-25 MHz, 1994.

Package: 132 pin PQFP (Plastic Quad Flat Package),
144 pin SQFP (Shrink Quad Flat Package),
die,
military (-55 - 125 C).

Technology: CMOS.

ID: step level A: DH = 0x23 (model ID, family ID), DL = 0x09 (revision).


2.26 AMD Am386 CPU

Intel i80386 CPU instruction compatible.
Same core and microcode as Intel i80386 CPU.


2.26.1 AMD Am386DX CPU

Low power.

Intel i80386DX CPU instruction/pin compatible.
Intel i80386DX IV CPU microcode.

March 1991.

16 MHz: 2-16 MHz.
20 MHz: 2-20 MHz.
25 MHz: 2-25 MHz.
33 MHz: 2-33 Mhz.
40 MHz: 2-40 MHz.

Technology: 0.8 micron CMOS.

ID: step level A: DH = 0x03 (model ID, family ID), DL = 0x05 (revision),
step level B: DH = 0x03 (model ID, family ID), DL = 0x08 (revision).


2.26.2 AMD Am386DXL CPU

Low power version of AMD Am386DX CPU.
Static core.
Intel i80386DX IV CPU microcode.

Intel i80386DX CPU upward pin compatible.

March 1991.

20 MHz.
25 MHz.
33 MHz.
40 MHz.

Technology: CMOS.

ID: step level A: DH = 0x03 (model ID, family ID), DL = 0x05 (revision),
step level B: DH = 0x03 (model ID, family ID), DL = 0x08 (revision).


2.26.3 AMD Am386DXLV CPU

Low power (SMM: System Management Mode), low voltage (3.3 V - 4.5 V) version
of AMD Am386DX CPU.
Static core.

Intel i80386DX CPU upward pin compatible.

October 1991.

25 MHz.
33 MHz.

Technology: CMOS.


2.26.4 AMD Am386SX CPU

Low power.
Extra pins assigned for power management.

Intel i80386SX CPU upward pin compatible.

July 1991.

16 MHz: 2-16 MHz.
20 MHz: 2-20 MHz.
25 MHz: 2-25 MHz, no longer available.
33 MHz: 2-33 MHz.
40 MHz: 2-40 MHz.

Technology: 0.8 micron CMOS.

ID: step level A1: DH = 0x23 (model ID, family ID), DL = 0x05 (revision),
step level B: DH = 0x23 (model ID, family ID), DL = 0x08 (revision).


2.26.5 AMD Am386SXL CPU

Low power version of AMD Am386SX CPU.
Static core.

July 1991.

20 MHz: 0-20 MHz.
25 MHz: 0-25 MHz.
33 MHz: 0-33 MHz.
40 MHz: 0-40 MHz.

Technology: CMOS.

ID: step level A1: DH = 0x23 (model ID, family ID), DL = 0x05 (revision),
step level B: DH = 0x23 (model ID, family ID), DL = 0x08 (revision).


2.26.6 AMD Am386SXLV CPU

Low power (SMM: System Management Mode), low voltage (3.3 V - 4.5 V) version
of AMD Am386SX CPU.
Static core.

October 1991.

20 MHz.
25 MHz.
33 MHz.

Technology: CMOS.


2.26.7 AMD Am386DE CPU

Embedded static version of the AMD Am386DX CPU.

25 MHz: 1995.
33 MHz: 1995.

Package: PQB132.

AMD Embedded Processors E86 Family.


2.26.8 AMD Am386SE CPU

Embedded static version of the AMD Am386SX CPU.

25 MHz: 1995.
33 MHz: 1995.

Package: PQB100.

AMD Embedded Processors E86 Family.


2.26.9 AMD Am386EM CPU

Intel i80386 CPU instruction compatible.
Extra features: 4 DMA channels with flyby and chaining support,
watchdog timer,
asynchronous & synchronous serial ports,
32 programmable I/O pins,
DRAM controller,
96 Mbyte address space,
JTAG support.

25 MHz: 1995.
33 MHz: 1995.

40 MHz: 1995.

Package: PQR132.

AMD Embedded Processors E86 Family.


2.27 IBM 386 CPU

Intel i80386 CPU instruction compatible.
Some instructions are executed faster than when executed by the
Intel i80386 CPU.


2.27.1 IBM 386SLC CPU

Low power.
Extra pins assigned for power management.

8 kbyte cache.
To be enabled via software.

October 1991.

16 MHz.
20 MHz.
25 MHz: 2.5 W.

Intel i80386SX CPU upward pin compatible (100 pin MQFP (Metal Quad Flat
Package)).

Technology: CMOS.
Die size: 161 mm2.

ID: step level A: DH = 0xA3 (model ID, family ID), DL = 0xXX (revision).


2.28 Chips & Technologies 386 CPU

Intel i80386 CPU instruction compatible, including undocumented
LOADALL386 instruction.
Own microcode (clean room).
Some instructions are executed faster than when executed by the
Intel i80386 CPU.


2.28.1 Chips & Technologies Super386 38600DX CPU

Co-operation with an appropriate NPX causes communication problems, which
causes the over-all performance to drop below that of an Intel i80386DX CPU
with NPX.

Intel i80386DX CPU pin compatible.

33 MHz.
40 MHz: 1650 mW.

No longer available.

Technology: CMOS.


2.28.2 Chips & Technologies 38605DX CPU

512 byte instruction cache.

32 bit internal data bus.
32 bit external data bus.
32 bit address bus.

Not Intel i80386DX CPU pin compatible.

No longer available.

Package: 144 pin PGA (Pin Grid Array).

Technology: CMOS.


2.28.3 Chips & Technologies 38600SX CPU

Intel i80386SX CPU pin compatible.

Never released.

Technology: CMOS.


2.29 IBM 386/486 hybrid CPU

Intel i80486 CPU instruction compatible, no FPU (Floating Point Unit).
Intel i80386 CPU bus interface.


2.29.1 IBM 486DLC CPU

Intel i80386 CPU core, enhanced by IBM.

16 kbyte cache: 4-way set-associative, write-through.
To be enabled via software (BIOS).

32 bit internal data bus.
32 bit external data bus.
32 bit address bus.

Not Intel i80386DX CPU pin compatible.

Technology: CMOS.


2.29.2 IBM 486DLC2 CPU

Clock doubled version of the IBM 486DLC CPU.

Intel i80386 CPU core, enhanced by IBM.

16 kbyte cache: 4-way set-associative, write-through.
To be enabled via software (BIOS).

Intel i80386DX CPU pin compatible.

November 1993.

33/66 MHz.

Technology: CMOS.


2.29.3 IBM 486SLC CPU

Intel i80386 CPU core, enhanced by IBM.

16 kbyte cache: 4-way set-associative, write-through.
To be enabled via software (BIOS).

32 bit internal data bus.

16 bit external data bus.
24 bit address bus.
Not Intel i80386SX CPU pin compatible.

16 MHz.
20 MHz.
20 MHz: 3.3 V, 1.0 W.
25 MHz.
25 MHz: 3.3 V, 1.3 W.

Technology: CMOS.

ID: step level A: DH = 0xA4 (model ID, family ID), DL = 0xXX (revision).


2.29.4 IBM 486SLC2 CPU

Clock doubled version of the IBM 486SLC CPU.
Low voltage: 3.3 V.

Intel i80386 CPU core, enhanced by IBM.

16 kbyte cache: 4-way set-associative, write-through, 16 byte line size.
To be enabled via software (BIOS).

Intel i80386SX CPU pin compatible (100 pin MQFP (Metal Quad Flat Package)).

December 1992.

16/32 MHz.
20/40 MHz: 1.7 W.
25/50 MHz: 1993, 2.3 W.
33/66 MHz: 1993.
40/80 MHz: 1993.

1.349E6 transistors.
Die size: 69 mm2.

ID: step level Ax: DH = 0xA4 (model ID, family ID), DL = 0x1X (revision),
step level Bx: DH = 0xA4 (model ID, family ID), DL = 0x2X (revision).


2.29.5 IBM 486BLX CPU (Blue Lightning)

Intel i80486 CPU core and microcode, no FPU.

16 kbyte cache: 4-way set-associative, write-through, 16 byte line size.
To be enabled via software (BIOS).

Low power (3.3 V).
Power management: SMM (System Management Mode).
Static core.

15 MHz.
20 Mhz.
25 MHz.
33 MHz.

Intel i80386DX CPU upward pin compatible / AMD Am386DXL/Am386DXLV CPU pin
compatible (132 pin MQFP (Metal Quad Flat Package)).

Technology: 0.8 micron CMOS.
Die size: 82 mm2.
1.4E6 transistors.


2.29.6 IBM 486BLX2 CPU (Blue Lightning)

Clock doubled version of the IBM 486BLX CPU.

15/30 MHz.
20/40 MHz.
25/50 MHz: 1993.
33/66 MHz: 1993.


2.29.7 IBM 486BLX3 CPU (Blue Lightning)

Clock tripled version of the IBM 486BLX CPU.

15/45 MHz.
20/60 MHz.
25/75 MHz: 1993.
33/100 MHz: 1993.

ID: step level A: DH = 0x84 (model ID, family ID), DL = 0xXX (revision).


2.30 Cyrix 386/486 hybrid CPU

Intel i80486 CPU instruction compatible, no FPU (Floating Point Unit).
Own core (clean room): not 100% compatible.
Intel i80386 CPU bus interface.


2.30.1 Cyrix Cx486DLC CPU

First generation 40 MHz CPUs had a bug: using a NPX (Cyrix FasMath EMC87 NPX,
Cyrix FasMath Cx83D87 NPX (until November 1991), IIT IIT-3C87 NPX) caused
crashes. These are caused by synchronisation errors in FSAVE and FSTOR
instructions. Later, improved CPUs have an AB prefix printed in the lower
right corner. The Cyrix FasMath 387+ NPX (European name for
Cyrix FasMath Cx83D87 NPX from November 1991) causes no trouble when
co-operating with a bad Cyrix Cx486DLC CPU.

Static core.

1 kbyte unified cache: write-through,
direct mapped / 2-way set-associative,
maximum of 4 non-cachable areas.
Hit rate: 65% without support of cache by motherboard, because of flush at
DMA,
85% with support of cache by motherboard (Cache Coherency Support).
To be enabled via software (BIOS).

Intel i80386DX CPU upward pin compatible.

June 1992.

25 MHz.
33 MHz.
40 MHz: 2800 mW.

Clock Skewing Correction Circuit.

Contains a fast extra 16x16 bit multiplier.

Extra pins assigned for cache, power and A20 management:
cache management: KEN#,
FLUSH#,
RPLSET#,
RPLVAL#,
power management: SUSP#,
SUSPA#,
A20 management: A20M#.

Technology: CMOS.

DIR0 register: 0x01.


2.30.2 Cyrix Cx486SLC CPU

Static core.

1 kbyte unified cache: write-through / write-back,
direct mapped / 2-way set-associative,
maximum of 4 non-cachable areas.
hit rate: 65% without support of cache by motherboard, because of flush at
DMA,
85% with support of cache by motherboard (Cache Coherency Support).
To be enabled via software (BIOS).

Intel i80386SX CPU upward pin compatible.

20 MHz: March 1992.
25 MHz: May 1992.
33 MHz.
40 MHz.

Clock Skewing Correction Circuit.

Contains a fast extra 16x16 bit multiplier.

Extra pins assigned for cache, power and A20 management:
cache management: KEN#,
FLUSH#,
RPLSET#,
RPLVAL#,
power management: SUSP#,
SUSPA#,
A20 management: A20M#.

Technology: CMOS.
0.6E6 transistors.
Die size: 108 mm2.

ID: step level A: DH = 0x04 (family ID), DL = 0x1X (revision),
DH = 0x04 (family ID), DL = 0x2X (revision).

No DIR0 register.


2.30.3 Cyrix Cx486SLC/e CPU

Low power (SMM: System Management Mode) version of Cyrix Cx486SLC CPU.
Static core.

December 1992.

25 MHz.
33 MHz.

Technology: CMOS.

DIR0 register: 0x00.


2.30.4 Cyrix Cx486SLC/e-V CPU

Low power (SMM: System Management Mode), low voltage (3.3 V) version of
Cyrix Cx486SLC CPU.
Static core.

December 1992.

20 MHz.
25 MHz.

Technology: CMOS.

DIR0 register: 0x00.


2.30.5 Cyrix Cx486DLC / Cx486SLC CPU incompatibilities

Same registers.
Same instruction set.
Differences in execution time of various instructions, average CPI (Cycles
Per Instruction) about equal.

Crashes with: NextStep,
DBOS 1.0 DOS extender of Salford FTN/386,
Fortran compiler.


2.30.6 Cyrix Cx486DLC2 CPU

Clock doubled version of the Cyrix Cx486DLC CPU.

Power Management: SMM (System Management Mode).
Static core.

DIR0 register: 0x03.


2.30.7 Cyrix Cx486SLC2 CPU

Clock doubled version of the Cyrix Cx486SLC CPU

Power Management: SMM (System Management Mode).
Static core.

November 1993.

25/50 MHz.

Technology: CMOS.

DIR0 register: 0x02.


2.30.8 Cyrix Cx486DRx CPU

DIR0 register: 0x05.


2.30.9 Cyrix Cx486SRx CPU

Intel i80486 CPU instruction compatible, no FPU (Floating Point Unit).

The chip is placed over the surface mounted 80386SX CPU. The original CPU is
disabled by using the FLOAT pin. Older 16 MHz 80386SX CPUs can not be
upgraded (Cyrix can supply a compatibility test program).

1 kbyte cache.

DIR0 register: 0x04.


2.30.10 Cyrix Cx486DRx2 CPU

Clock doubled version of the Cyrix Cx486DRx CPU.

Incompatibilities: AT&T / Olivetti 386DX-16 and 386DX-20 systems,
Sun i386 systems,
Memorex 386 systems,
IBM PS/2 Model 70/16 MHz (85 ns memory required),
early Compaq Deskpro 386/16 MHz systems with 287 NPX (NPX
to be removed).

September 1993.

16/32 MHz.
20/40 MHz: heat sink.
25/50 MHz: heat sink.
33/66 MHz.

Technology: CMOS.

DIR0 register: 0x07.


2.30.11 Cyrix Cx486SRx2 CPU

Clock doubled version of the Cyrix Cx486SRx CPU.

December 1993.

16/32 MHz.
20/40 MHz.
25/50 MHz.

Technology: CMOS.

DIR0 register: 0x06.


2.30.12 Cyrix Cx486DRu CPU

Direct Replacement Unit.
In fact a Cyrix Cx486DLC CPU with some additional hardware on a little PCB
that fits in a PGA (Pin Grid Array).

DIR0 register: 0x09.


2.30.13 Cyrix Cx486SRu CPU

DIR0 register: 0x08.


2.30.14 Cyrix Cx486DRu2 CPU

Clock doubled version of the Cyrix Cx486DRu CPU.

16/32 MHz.
20/40 MHz.
25/50 MHz.

DIR0 register: 0x0B.


2.30.15 Cyrix Cx486SRu2 CPU

Clock doubled version of the Cyrix Cx486SRu CPU.

DIR0 register: 0x0A.


2.31 Texas Instruments 386/486 hybrid CPU

2.31.1 Texas Instruments TI486DLC CPU

Cyrix Cx486DLC CPU.

ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

2.31.2 Texas Instruments TI486SLC CPU

Cyrix Cx486SLC CPU.

ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

2.31.3 Texas Instruments TI486SXL-S-GA CPU (Potomac)

Intel i80486 CPU instruction compatible, no FPU (Floating point Unit).
Intel i80386DX CPU bus interface.

8 kbyte cache: write-through, 2-way set-associative, 1024 sets,
4 bytes per line.

40 MHz: february 1994.

Package: ceramic PGA (Pin Grid Array).

Technology: CMOS.

ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.


2.31.4 Texas Instruments TI486SXL-VS-GA CPU (Potomac)

Low power (3.3 V) version of the Texas Instruments TI486SXL-S-GA CPU.

33 MHz: february 1994.

Technology: CMOS.

ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.


2.31.5 Texas Instruments TI486SXL2-S-GA CPU (Potomac)

Clock doubled version of the Texas Instruments TI486SXL-S-GA CPU.

20/40 MHz: february 1994.
25/50 MHz: february 1994.

Technology: CMOS.

ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.


2.31.6 Texas Instruments TI486SXL2-VS-GA CPU (Potomac)

Clock doubled, low power (3.3 V) version of the
Texas Instruments TI486SXL-S-GA CPU.

20/40 MHz: february 1994.

Technology: CMOS.

ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.


2.31.7 Texas Instruments TI486SXLC-PAF CPU (Potomac)

Intel i80486 CPU instruction compatible, no FPU (Floating Point Unit).
Intel i80386SX CPU bus interface.

8 kbyte cache: write-through, 2-way set-associative, 1024 sets,
4 bytes per line.

33 MHz: february 1994.

Package: QFP (Quad Flat Package).

Technology: CMOS.

ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.


2.31.8 Texas Instruments TI486SXLC-V-PAF CPU (Potomac)

Low power (3.3 V) version of the Texas Instruments TI486SXLC-PAF CPU.

25 MHz: february 1994.
33 MHz: february 1994.

Technology: CMOS.

ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.


2.31.9 Texas Instruments TI486SXLC2-PAF CPU (Potomac)

Clock doubled version of the Texas Instruments TI486SXLC-PAF CPU.

20/40 MHz: february 1994.
25/50 MHz: february 1994.

Technology: CMOS.

ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.


2.31.10 Texas Instruments TI486SXLC2-V-PAF CPU (Potomac)

Clock doubled, low power (3.3 V) version of the
Texas Instruments TI486SXLC-PAF CPU.

20/40 MHz: february 1994.

Technology: CMOS.

ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).

DIR0 register: 0xFE.


2.31.11 Texas Instruments announcements

Rio Grande series: Potomac series follow-up.

Aad Offerman

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Jul 27, 1998, 3:00:00 AM7/27/98
to


Hello,

The HTML version of the latest Personal Computer CHIPLIST, version 9.9.5, is
now available on WWW. Take a look at:

http://einstein.et.tudelft.nl/~offerman/chiplist.html

Enjoy.

Salut, Aad Offerman

Aad Offerman

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Jul 27, 1998, 3:00:00 AM7/27/98
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Archive-name: pc-hardware-faq/chiplist/part4
Last-modified: 1998/07/26
Version: 9.9.5


2.42 Intel Pentium CPU

2-issue 5-stage superscalar with 8-stage pipelined FPU (Floating Point Unit).
Intel i80486 CPU upward instruction compatible.

Multiprocessor support.
Upgrading: adding another Intel Pentium CPU.

Parity checking at busses.

Branch prediction (BTB: Branch Target Buffer).

8 kbyte instruction cache, 8 kbyte data cache (Harvard architecture).
Both 2-way set-associative, write-back, no write-allocate.

32 bit internal data bus (CPU - MMU (Memory Management Unit, including cache))
64 bit external data bus (MMU (Memory Management Unit, including cache)
- memory).
32 bit address bus.

Package: 296 pin PGA (Pin Grid Array).

Label:
processor type, clock speed,
A80502133: 133 MHz Pentium,
stepping and quality,
SY022/SSS:
SY022: lithography mask number,
s-spec (part characteristics): SK, SU, SX, SY, SZ,
S: Standard voltage (3.135 - 3.6 V),
V (VRE): narrowed voltages 3.4 - 3.6 V,
S: Standard timing, M: Minimum Valid MD timing,
S: Standard configuration, U: Uniprocessor only,
embossed iPP mark: carried by all Pentium CPU's at 90 MHz and faster,
most 75 MHz Pentium CPU's carry only the i75 mark,
90 MHz and faster Pentium CPU's with the i75 mark are
most likely fake,
iCOMP index,
serial number,
6044482-0591: number and serial number,
country of manufacture,
MALAY: Malayasia.

In October 1994 Dr. Thomas R. Nicely, Professor of Mathematics at the
Lynchburg College, Lynchburg, Virginia (nic...@acavax.lynchburg.edu), reported
a bug present in the FPU of all Intel Pentium CPUs. The double precision part
of the mantissa is not computed correctly when dividing in some areas of the
mantissa space of the divisor. The bug is fixed in Intel Pentium CPUs produced
after November 1994.


2.42.1 Intel Pentium P5 CPU

60 MHz (Intel Pentium 510\60 CPU): 5 V, March 1993, 17-13 W, iCOMP 510.
66 MHz (Intel Pentium 567\66 CPU): 5 V, 16-13 W, iCOMP 567, 64.5 SPECint92,
56.9 SPECfp92 (First 66 MHz CPUs had
heat troubles and were released as 60 MHz
items).

Package: 273 pin PGA (Pin Grid Array) (Socket 4: 273 pins, 5 V).

Technology: 0.8 micron biCMOS.
3.1E6 transistors.
Die size: 18 x 16 mm.

ID: step level Ax: DH = 0x05 (family ID), DL = 0x0X (model ID, revision),
step level B1: DH = 0x05 (family ID), DL = 0x13 (model ID, revision),
step level C1: DH = 0x05 (family ID), DL = 0x15 (model ID, revision),
step level D1: DH = 0x05 (family ID), DL = 0x17 (model ID, revision).

CPUID: step level Ax: family = 0x5, model = 0,
step level Bx: family = 0x5, model = 1.

Model 1, revision 7: FDIV bug fixed.

60 MHz: 80500.
60, 66 MHz: 80501.


2.42.2 Intel Pentium P54C CPU

Upgrading: Intel Pentium P54M OverDrive (2 CPUs co-operating),
Intel Pentium P54CT CPU.

50/75 MHz (Intel Pentium 610\75 CPU) (notebooks, P54T): 3.3 V, August 1994,
package: 320 pin TCP, iCOMP 610.
60/90 MHz (Intel Pentium 735\90 CPU): 3.3 V, March 1994, iCOMP 735.
66/100 MHz (Intel Pentium 815\100 CPU): 3.3 V, March 1994, iCOMP 815.

Package: 296 pin PGA (Pin Grid Array) (Socket 5: 320 pins, 3.3 V).

Technology: 4-layer metal, 0.6 micron biCMOS.
3.1E6 transistors.
Die size: 12 x 13 mm.

60/120 MHz (Intel Pentium 1000\120 CPU, Intel Pentium P54CQS CPU):
no multi-processor features, 3.3 V, March 1995, iCOMP 1000, step level C2.

Package: 296 pin PGA (Pin Grid Array) (Socket 5).

Technology: 0.35 micron CMOS.
3.1E6 transistors.
Die size: 90 mm2.

Intel Pentium P54CS CPU.

66/133 MHz (Intel Pentium 1110\133 CPU):
package: 296 pin PGA (Pin Grid Array) (Socket 5), iCOMP 1110.
60/150 MHz: 3.3 V, iCOMP 1195.
66/166 MHz: 3.3 V, iCOMP 1340.
66/200 MHz: 3.3 V.

Package: 296 pin PGA (Pin Grid Array) (Socket 7).

Technology: 0.35 micron CMOS.
3.1E6 transistors.
Die size: 90 mm2.

The multiplier can be 1.5, 2, 2.5, or 3.

ID: step level A: DH = 0x05 (family ID), DL = 0x2X (model ID, revision),
step level B1: DH = 0x05 (family ID), DL = 0x21 (model ID, revision),
step level B3: DH = 0x05 (family ID), DL = 0x22 (model ID, revision),
step level B5: DH = 0x05 (family ID), DL = 0x24 (model ID, revision),
step level C1: DH = 0x05 (family ID), DL = 0x25 (model ID, revision),
step level C2 (120 MHz): DH = 0x05 (family ID),
DL = 0x25 (model ID, revision),
P54CQS, 120 MHz: DH = 0x05 (family ID), DL = 0x25 (model ID, revision),
P54LM, 2.9 V, step level Ax: DH = 0x05 (family ID),
DL = 0x25 (model ID, revision).

CPUID: family = 0x5, model = 0x2.

Model 2, revision 5: FDIV bug fixed.

60, 66 MHz: 80501.
50/75, 60/90, 66/100, 60/120, 66/133 MHz: 80502.

Embedded Processor Module:
EMBMOD133: 66/133 MHz Pentium with 82430HX PCIset.


2.43 Intel OverDrive CPU for Intel Pentium CPU

2.43.1 Intel Pentium P54M CPU

Pentium OverDrive processor for Intel Pentium P54C CPU.

Technology: CMOS.

ID: DH = 0x25 (model ID, family ID), DL = 0x2X (revision).

2.43.2 Intel Pentium OverDrive CPU

Pentium OverDrive processor for Intel Pentium P5 CPU.

60/120 and 66/133 MHz (P5T, PODP5V120/133): for 60 and 66 MHz systems,
iCOMP 877/978.

3.3 V core (voltage regulator), 5 V I/O.

Package: 273 pin PGA (Pin Grid Array) (Socket 4).

Technology: 0.8 micron CMOS.
3.1E6 transistors.

Pentium P54CT(A) OverDrive processor for Intel Pentium P54C CPU.

50/125 MHz (PODP3V125): for 50/75 MHz systems, iCOMP 1070.
60/150 MHz (PODP3V150): for 60/90 MHz systems, iCOMP 1176.
66/166 MHz (PODP3V166): for 66/100 MHz systems, iCOMP 1308.

3.3 V.

Voltages: 3.3 V: 3.135 - 3.600 V.

Package: 320 pin PGA (Pin Grid Array) (Socket 5/7).

Technology: 0.35 micron CMOS.
3.1E6 transistors.
Die size: 90 mm2.


2.44 AMD K5 CPU (K86 series)

Intel Pentium CPU compatible.

X86 to RISC Operation (ROP) translation.

Superscalar: 5-stage,
3 integer pipelines, FP pipeline.

Cache: 16 kbyte instruction with predecode unit, 8 kbyte data
(Harvard architecture), MESI architecture.

Dynamic, block oriented, branch prediction with speculative execution.

Package: 296 pin SPGA (Pin Grid Array) (Socket 7).

Technology: 3.3 V, 3-layer metal, 0.5 micron CMOS (Fab 25, Texas),
0.35 micron CMOS (first quarter 1996).


2.44.1 AMD 5k86 K5 CPU (K86 series)

AMD K5-PR75 CPU (SSA, model 0): 50/75 MHz, March 1996, die size: 177 mm2.
AMD K5-PR90 CPU (SSA, model 0): 60/90 MHz.
AMD K5-PR100 CPU (SSA, model 0): 66/100 MHz.
AMD K5-PR120 CPU (5k86, model 1): 60/90 MHz.
AMD K5-PR133 CPU (5k86, model 1): 66/100 MHz.
AMD K5-PR150 CPU (5k86, model 2): 60/105 MHz.
AMD K5-PR166 CPU (5k86, model 2): 66/116 MHz, March 1997.
AMD K5-PR200 CPU (5k86, model 3): 66/133 MHz, never released.

No longer manufactured from mid 1997.

3.52 V.

Technology: 0.35 micron.
4.3E6 transistors.
Die size: 161 mm2.

The multiplier can not be changed.


2.44.2 AMD 5k86 SSA/5 CPU (K86 series)

Pre-release AMD 5k86 K5 CPU: more internal wait states,
incomplete BTB (Branch Target Buffer).

Features: VME, I/O Breakpoints, TSC (Time Stamp Counter), Machine Check.

133 MHz: May 1996.

Step level: 0x50.


2.45 Cyrix 586 CPU

Intel Pentium CPU compatible.
Clock doubled/tripled.

16 kbyte unified cache: write-back, 4-way set-associative.

Power management: SMM (System Management Mode),
hardware suspend,
stop-clock,
FPU auto-idle.

50 MHz.
100 MHz (announced: third quarter 1995).
120 MHz.

Not available anymore due to compatibility problems.

3.3 V, 5 V I/O.

Superscalar: 2-issue, 7-stage.
Branch prediction, branch target cache.
Load/store unit.
FPU: 4 64 bit write buffers.

Package: 296 pin PGA.

Technology: 0.5 micron CMOS (IBM, SGS-Thomson).

DIR0 register: 0x30.

Cyrix M1 CPU.


2.45.1 Cyrix Cx5x86 CPU

Primary cache: 16 kbyte unified, write-back, 4-way set-associative.

Power management: SMM (System Management Mode),
hardware suspend, stop clock,
FPU auto-idle.

50/100, 33/100 (Cyrix Cx5x86-100GP/QP CPU): 3.45 V, July 1995.
40/120 (Cyrix Cx5x86-120GP/QP CPU): 3.45 V.

The multiplier can be 2 or 3.

In general practice, even faster than Intel's Pentium Pro CPUs (Cyrix
optimized for 16 bit code, Intel optimized the Pentium and Pentium Pro CPUs
for 32 bit code).

Package: 168 pin PGA (Pin Grid Array) (GP),
208 pin QFP (Quad Flat Package) (QP).

1.9E6 transistors.
Die size: 144 mm2.


2.46 NexGen Nx586/Nx587 CPU chipset

Intel Pentium CPU instruction compatible, no FPU (Floating Poin Unit).
RISC (Reduced Instruction Set Computer): RISC86: interpreting (hardware)
Intel Pentium CPU instruction set.

Runs internally at 4 V; Compatibility with 5 V motherboard provided through
the bus interface chip.

16 kbyte instruction cache, 16 kbyte data cache (Harvard architecture).
External level 2 cache controller for 256 kbyte or 1 Mbyte.

NexGen Nx586 CPU: 60 MHz,
66 MHz.
NexGen Nx587 NPX: 60 MHz,
66 MHz.

March 1994.

NexGen NxVL Vesa Local Bus interface: 60 MHz,
66 Mhz.
NexGen NxPCI PCI Bus interface: October 1995.

Superscalar: 2 integer units,
FP adder (2 cycles),
FP multiplier (2 cycles).
Branch prediction.

NexGen Nx586 CPU: 4 V, 9 W, 3.5E6 transistors, die size: 118 mm2,
0.5 micron CMOS.
NexGen Nx587 NPX: 4 V, 1.1 W, 0.7E6 transistors, 0.5 micron CMOS.
NexGen NxVL Vesa Local Bus interface: 5 V, 1.0 W, 0.5 micron CMOS.

70 MHz (PR75): September 1994.
80 MHz: September 1994.
90 MHz: September 1994.
100 MHz.
133 MHz: December 1994.

Manufactured by IBM.


2.47 Intel Pentium Pro P6 CPU

Upward compatible with all previous iapx CPUs (RISC core with X86
translation).

Superpipelined superscalar: 3-issue, 12-stage, instruction pool,
fetch/decode unit,
dispatch/execution unit (2 AGU (Address Generation Unit): 1 load, 1 store,
1 JEU (Jump Execution Unit), 2 IEU (Integer Execution Unit),
1 FEU (Floating Execution Unit)), retire unit.
ECC (Error Correcting Code).
Fault Analysis & Recovery.
Functional Redundancy Checking.
Multi-branch prediction, data flow analysis, speculative execution.

Level 1 cache: 8 kbyte instruction, 8 kbyte data (Harvard architecture).
Level 2 cache: 256/512 kbyte or 1 Mbyte, MESI architecture, custom SRAM.
4 Gbyte cachable main memory.

Multi-processor support.
2 or 4 Intel Pentium Pro CPUs can co-operate in a SMP (Symmetric
Multi-Processor) environment.
The speed-up of a 2-CPU configuration is excellent. The speed-up of a 4-CPU
configuration is relatively poor, probably due to too small caches causing too
many cache flushes.

60/120 MHz.
66/133 MHz (engineering sample): 256 kbyte level 2 cache, 2.9 V, 3.1 V, 14 W.
60/150 MHz: 256 kbyte level 2 cache, 3.1 V, November 1995, 23.0 W.

Technology: 0.6 micron biCMOS, precharged domino logic.
5.5E6 transistors.
Die size: 306 mm2.

66/166 MHz: 512 kbyte level 2 cache, November 1995, 27.5 W.
60/180 MHz: 256 kbyte level 2 cache, November 1995, 24.8 W.
66/200 MHz: 256 kbyte level 2 cache, 3.3/3.5 V, November 1995, 27.3 W.
66/200 MHz: 512 kbyte level 2 cache, November 1995, 32.6 W.

3.3 V.

Package: 387 pin CPGA (Ceramic Pin Grid Array) (Socket 8).
This package contains two dies: the processor and the level 2 cache
(dual-cavity package), interconnected by the DIB (Dual Independent Bus).

Technology: 0.35 micron CMOS.
5.5E6 transistors.
Die size: 195 mm2.

ID: DH = 0x06 (model ID, family ID), DL = 0xXX (revision).

Pentium Pro and Pentium II processors contain a bug in the FPU (Floating Point
Unit) (Dan-0411). The conversion of certain large negative numbers into
integers sometimes fails to detect an overflow. Software work-arounds are
available.

66/200 MHz: 1 Mbyte level 2 cache, 3.3 V, August 1997, 43 W.
66/200 MHz: 1 Mbyte level 2 cache,
3.2 V (VID (Voltage Identification) to be ignored), August 1997,
40 W.

Voltages: 3.1 V: 2.945 - 3.255 V,
3.2 V: 3.1 - 3.3 V,
3.3 V: 3.135 - 3.465 V,
3.5 V: 3.325 - 3.675 V.

Technology: 0.35 micron biCMOS.

The multiplier can be 2.5, 3, 3.5, or 4.


2.47.1 Intel Pentium Pro P6L CPU

Intel Pentium Pro P6 CPU without level 2 cache.


2.48 Intel OverDrive P6 CPU

2.48.1 Intel OverDrive P6T CPU

P6 Microarchitecture Core (Pentium II Deschutes).

300 MHz: 23.8 W (announced).
333 MHz: 26.3 W (announced).

2.5 V core, 3.3 V I/O.

Voltages: 2.5 V: 2.375 - 2.625 V,
3.3 V: 3.135 - 3.465 V.

Package: 387 pin PGA (Pin Grid Array) (Socket 8).

Technology: 0.25 micron CMOS.
7.5E6 transistors.
Die size: 131 mm2.

ID: DH = 0x16 (model ID, family ID), DL = 0xXX (revision).


2.49 IBM 6x86 CPU

Cyrix 6x86 CPUs.


2.49.1 IBM 6x86 CPU

IBM 266x86-2V2100GB CPU: 50/100 MHz.
IBM 266x86-2V2110GB CPU: 55/110 MHz.
IBM 266x86-2V2120GB CPU: 60/120 MHz.
IBM 266x86-2V2133GB CPU: 66/133 MHz.

March 1996.

3.3 V.

CPUID: family=0x5, model=0x3, step level=0.

IBM 6x86-P120+ CPU (IBM 266x86-2V2P120GE CPU): 50/100 MHz, 3.3 V core,
5 V tolerant I/O.
IBM 6x86-P133+ CPU (IBM 266x86-2V2P133GE CPU): 55/110 MHz, 3.3 V core,
5 V tolerant I/O.
IBM 6x86-P150+ CPU (IBM 266x86-2V2P150GE CPU): 60/120 MHz, 3.3 V core,
5 V tolerant I/O.
IBM 6x86-P150+ CPU (IBM 266x86-2V7P150GE CPU): 60/120 MHz, 3.5 V core,
5 V tolerant I/O.
IBM 6x86-P166+ CPU (IBM 266x86-2V2P166GE CPU): 66/133 MHz, 3.3 V core,
5 V tolerant I/O.
IBM 6x86-P166+ CPU (IBM 266x86-2V7P166GE CPU): 66/133 MHz, 3.5 V core,
5 V tolerant I/O.
IBM 6x86-P200+ CPU (IBM 266x86-2V7P200GE CPU): 75/150 MHz, 3.5 V core,
5 V tolerant I/O.

November 1996.

Package: 296 pin SPGA (Pin Grid Array) (P54C socket compatible).

DIR0 register: 0x31, DIR1 register: 0x1X / 0x2X.


2.49.2 IBM 6x86L CPU

Low power version (25 % reduction) of the IBM 6x86 CPU.
2.8 V core, 3.3 V I/O, 5 V tolerant I/O.

IBM 6x86L-P120+ CPU: 50/100 MHz.
IBM 6x86L-P133+ CPU: 55/100 MHz.
IBM 6x86L-P150+ CPU (IBM 266x86L-2VAP150GB CPU): 60/120 MHz.
IBM 6x86L-P166+ CPU (IBM 266x86L-2VAP166GB CPU): 66/133 MHz.
IBM 6x86L-P200+ CPU (IBM 266x86L-2VAP200GB CPU):
75/150 MHz, technology: 5-layer metal, 0.44 micron IBM CMOS.

This CPU uses two power supplies: one supply (2.8 V) is for the core, and the
other (3.3 V) is for the I/O interface.

Package: 296 pin SPGA (Pin Grid Array) (Socket 7 compatible).

DIR0 register: 0x31, DIR1 register: 0x2X.


2.50 Cyrix 6x86 CPU

Pentium Pro class CPU (RISC core with X86 translation).

In general practice, even faster than Intel's Pentium Pro CPUs (Cyrix
optimized for 16 bit code, Intel optimized the Pentium and Pentium Pro CPUs
for 32 bit code). However, due to the slow FPU, the performance of floating
point intensive applications like the game Quake is low.

Due to the first chips' sensitivity for reflections on the busses, Microsoft
decided to turn off the primary cache for Window NT 4.0 for pre revision 2.7
chips. Registered Windows NT 4.0 users can obtain a processor replacement from
Cyrix, or download a patch.

Superpipelined superscalar: 2-issue, 7-stage; 2 integer units,
FPU (Floating Point Unit).
Features: register renaming, out-of-order execution, data dependancy removal,
multi-branch prediction, speculative execution.
TLB (Translation Look-aside Buffer): 128-entry L1, 8-entry victim.
BTB (Branch Target Buffer): 256-entry, 4-way set-associative,
512-entry branch history table.

16 kbyte unified cache: write-back/write-through, 4-way set-associative,

dual-ported, MESI architecture.
Pipelined burst-mode reads and writes.
256 byte instruction cache: fully-associative.

Multiprocessing support: SLiC/MP, OpenPIC interrupt architecture.

Selectable 2x/3x clock multiplier.

Power management: SMM (System Management Mode),
Suspend Mode,
FPU auto-idle.

Cyrix 6x86 CPU: 3.3 V (C016) or 3.52 V (C028) core,
or voltage switching supporting both, 5 V tolerant I/O,
from revision 2.7 less power consumption.

40/80 MHz (Cyrix 6x86-PR90+ CPU): 3.3 V.
50/100 MHz (Cyrix 6x86-PR120+GP CPU): 3.3 V.
55/110 MHz (Cyrix 6x86-PR133+GP CPU): 3.3 V.
60/120 MHz (Cyrix 6x86-PR150+GP CPU): 3.3 or 3.52 V.
66/133 MHz (Cyrix 6x86-PR166+GP CPU): 3.3 or 3.52 V.
75/150 MHz (Cyrix 6x86-PR200+ CPU): 3.52 V.

Technology: 0.65 micron CMOS.
3.0E6 transitors.
Die size: 210 mm2.

Cyrix M1 CPU.

Cyrix 6x86L CPU (low power): 2.8 V core, 3.3 V I/O.

50/100 MHz (Cyrix 6x86L-PR120+ CPU).
55/110 MHz (Cyrix 6x86L-PR133+ CPU).
60/120 MHz (Cyrix 6x86L-PR150+ CPU).
66/133 MHz (Cyrix 6x86L-PR166+ CPU).
75/150 MHz (Cyrix 6x86L-PR200+ CPU): technology: 0.44 micron CMOS.

Technology: 0.5 micron CMOS.
3.0E6 transistors.
Die size: 169 mm2.

Package: 296 pin PGA (Pin Grid Array) (Socket 7),
296 pin CPGA (Ceramic Pin Grid Array) (Socket 7).

Cyrix M1R CPU.


2.51 NexGen Nx686 CPU

Pentium Pro class CPU (RISC core with X86 translation).

Cache: 16 kbyte instruction, 32 kbyte data (Harvard architecture).
Level 2 cache controller.

180 MHz.

Technology: 5-layer metal, 0.35 micron IBM CMOS.
6E6 transistors.


2.52 Intel MMX technology

In 1994 Intel started the NSP initiative (Native Signal Processing), but that
project failed due to software problems. In 1995 the MMX project was started.

MMX (Matrix Math eXtensions, Multi-Media eXtensions): 57 SIMD instructions
(Single-Instruction, Multiple-Data) for audio, video, and communication.
Multi-media code of applications need to be rewritten and recompiled to take
advantage of the MMX instruction set.
The MMX technology has been licenced to AMD and Cyrix.

The KNI technology (Katmai New Instructions, "MMX2"), adding another 70
instructions for 3D applications, will be available at the first quarter of
1999.

Intel MMX WWW server: http://www.mmx.com/

Dedicated multi-media chips:
Philips: TriMedia:
VLIW (Very Long Instruction Word),
Chromatic Research: Mpact:
a combined 486 and Mpact processor by SGS-Thomson will be available in the
second quarter of 1998, also produced by Toshiba and LG Semicon,
Samsung.
4 to 10 times faster than MMX processors, prices around $50.


2.53 Intel Pentium/MMX P55C CPU

Two MMX execution units.

16 kbyte instruction cache, 16 kbyte data cache (Harvard architecture).

66/166 MHz: January 1997.
66/200 MHz: January 1997.
66/233 MHz: June 1997.
66/266 MHz (announced: end 1997).

The multiplier can be 2, 2.5, 3, or 3.5.

2.8 V, 3.3 V I/O.

Both Intel MMX processors and the Cyrix 6x86MX CPU use the FPU for the MMX
implementation, resulting in tens of stall cycles while switching between
integer, FPU, and MMX code.

Embedded Processor Module:
EMBMOD166: 66/166 MHz Pentium/MMX with 82430HX PCIset,
announced: first quarter 1998.

Runs MMX aware multi-media applications about 60 % faster than ordinary
Intel Pentium CPU.

Package: 296 pin PPGA (Plastic Pin Grid Array) (Socket 7).

Technology: 4-layer metal, 0.35 micron CMOS.
4.5E6 transistors.
Die size: 141 mm2.


2.54 Intel Mobile Pentium/MMX CPU

Two MMX execution units.

66/133 MHz.
50/150 MHz.
66/166 MHz.
66/200 MHz.

2.45 V, 3.3 V I/O.

66/166 MHz: January 1998, 2.9 W.
66/200 MHz: September 1997, 3.4 W.
66/233 MHz: September 1997, 3.9 W.
66/266 MHz: 2.0 V, January 1998, 5.3 W.

4.5E6 transistors.
Die size: 95 mm2.

1.8 V, 2.5 V I/O (Voltage Reduction Technology).

Tillamook.

Package: Mobile Module,
320 pin TCP (Tape Carrier Packaging).

Technology: 5 layer metal, 0.25 micron CMOS.


2.55 Intel Pentium/MMX OverDrive CPU

Pentium/MMX P54CTB OverDrive processor for Intel Pentium CPUs.

2.8 V core (voltage regulator), 3.3 V I/O.

50/125 MHz: for 75, 100 MHz systems.
60/150 MHz: for 90, 120 MHz systems.
66/166 MHz (BPODPMT66X166):
for 75 (to 50/125), 90 (to 60/150), 100, 133 MHz systems.
60/180 MHz (BPODPMT66X180):
for 75 (to 50/150), 90, 120, 150 MHz systems, August 1997.
66/200 MHz (BPODPMT66X200):
for 100, 133, 166 MHz Socket 7 systems, August 1997.

Voltages: 3.3 V: 3.135 - 3.6 V.

Package: 320 pin PGA (Pin Grid Array) (Socket 5/7).

Technology: 4-layer metal, 0.35 micron CMOS.
4.5E6 transistors.
Die size: 141 mm2.


2.56 Intel Pentium II CPU

2.56.1 Intel Pentium II CPU

Pentium Pro class CPU with MMX technology.

Level 1 cache: 16 kbyte instruction, 16 kbyte data (Harvard architecture),
non-blocking.
Level 2 cache: 512 kbyte, 4-way set-associative, non-blocking, BSRAM.
512 Mbyte cachable main memory.

SMP (Symmetric Multi-Processor) support for 2 CPUs through GTL+ bus.

Two MMX execution units.

66/233 MHz: April 1997, 34.8 W, iCOMP 2.0 267, SPECint95 9.38, SPECfp95 7.4,
Intel Media Benchmark 364.13.
66/266 MHz: April 1997, 38.2 W, iCOMP 2.0 303, SPECint95 10.7, SPECfp95 8.17,
Intel Media Benchmark 412.31.
66/300 MHz: ECC (Error Correcting Code), 43.0 W, iCOMP 2.0 332,
SPECint95 11.9, SPECfp95 8.82, Intel Media Benchmark 459.08.

2.8 V core, 3.3 V I/O.

Voltages: 2.8 V: 2.73 - 2.9 V,
3.3 V: 3.135 - 3.465 V.

From July 1997 the secondary cache is supplied with ECC (Error Correcting
Code).

Package: 242 pin SEC module (Single Edge Contact) (Slot 1).
The SEC module consists of a PCB containing the processor chip and the level 2
cache chips. Compared to the Intel Pentium Pro P6 CPU that combines the
processor die and level 2 cache die in a single package (dual-cavity package),
the DIB (Dual Independent Bus) is clocked at only half the speed.

The clock multiplier can be 3.5, 4, 4.5, 5.

Technology: 4 layer metal, 0.35 micron CMOS.
7.5E6 transitors in core.
Die size: 203 mm2.

Pentium Pro and Pentium II processors contain a bug in the FPU (Floating Point
Unit) (Dan-0411). The conversion of certain large negative numbers into
integers sometimes fails to detect an overflow. Software work-arounds are
available.

Klamath.


2.56.2 Intel Pentium II CPU

P6 Microarchitecture Core.
Dynamic Execution: multiple branch prediction, dataflow analysis,
speculative execution.
MMX.

Level 1 cache: 16 kbyte instruction, 16 kbyte data (Harvard architecture),
non-blocking.
Level 2 cache: 512 kbyte, 4-way set-associative, non-blocking, BSRAM.
4 Gbyte cachable main memory (512 Mbyte by step level dA0, 333 MHz version).
ECC (Error Correcting Code).

SMP (Symmetric Multi-Processor) support for 2 CPUs (Nightshade architecture).

66/333 MHz: January 1998, 23.6 W, iCOMP 2.0 366, SPECint95 13.0,
SPECfp95 9.55, Intel Media Benchmark 498.79.

2.0 V core, 3.3 V I/O.

Voltages: 2.0 V: 1.93 - 2.1 V,
3.3 V: 3.135 - 3.465 V.

100/350 MHz: April 1998, 24.5 W, iCOMP 2.0 386, SPECint95 13.9,
SPECfp95 11.20, Intel Media Benchmark 534.61.
100/400 MHz: April 1998, 27.9 W, iCOMP 2.0 440, SPECint95 15.8,
SPECfp95 12.40, Intel Media Benchmark 601.10.
100/450 MHz: announced: September 1998.

The multiplier can not be changed.

2.0 V core, 3.3 V I/O.

Voltages: 2.0 V: 1.9 - 2.1 V,
3.3 V: 3.135 - 3.465 V.

ID (333 MHz): step level dA0: family ID 6, model ID 5, revision 0,
step level dA1: family ID 6, model ID 5, revision 1.

Package: 242 pin SEC module (Single Edge Contact) (Slot 1).

Technology: 5 layer metal, 0.25 micron CMOS.
7.5E6 transitors in core.
Die size: 130.9 mm2.
On-die thermocouple for temperature monitoring.

Deschutes.


2.56.3 Intel Pentium Celeron CPU

Low-end Intel Pentium II CPU for Basic PC.

P6 Microarchitecture Core.
Dynamic Execution: multiple branch prediction, dataflow analysis,
speculative execution.
MMX.

Level 1 cache: 16 kbyte instruction, 16 kbyte data (Harvard architecture),
non-blocking.
No level 2 cache.

No multi-processor support.

66/266 MHz: April 1998, 16.7 W, iCOMP 2.0 213, Business Winstone 98 14.7,
Intel Media Benchmark 305.36, 3D Winbench 98 437.
66/300 MHz: June 1998.
66/333 MHz (announced: fourth quarter 1998).
100 MHz bus (announced: first half 1999).

The multiplier can not be changed.

2.0 V.

Voltages: 2.0 V: 1.9 - 2.1 V.

Package: SEPP (Single Edge Processor Package) (Slot 1).

Technology: 5 layer metal, 0.25 micron CMOS.
7.5E6 transitors in core.
Die size: 130.9 mm2.

Covington.

On-chip level 2 cache: 128 kbyte, 4-way set-associative, non-blocking, BSRAM.

66/300 MHz (announced: third quarter 1998).
66/333 MHz (announced: fourth quarter 1998).
66/366 MHz (announced: first half 1999).

Package: SEPP (Single Edge Processor Package) (Slot 1),
370 pin Socket.

Mendocino.


2.56.4 Intel Mobile Pentium II CPU

P6 Microarchitecture Core.
Dynamic Execution: multiple branch prediction, dataflow analysis,
speculative execution.
MMX.

Level 1 cache: 16 kbyte instruction, 16 kbyte data (Harvard architecture),
non-blocking.
Level 2 cache: 512 kbyte, 4-way set-associative, non-blocking, BSRAM.
4 Gbyte cachable main memory.
ECC (Error Correcting Code).

66/233 MHz: April 1998, 10.6 W.
66/266 MHz: April 1998, 12.1 W.
66/300 MHz: announced: end 1998.
66/333 MHz: announced: begin 1999.

1.7 V.

Voltages: 1.7 V: 1.58 - 1.82 V.

Package: Mobile Module,
Mini Cartridge.

Technology: 5 layer metal, 0.25 micron CMOS.
7.5E6 transitors in core.
Die size: 130.9 mm2.


2.56.5 Intel Pentium II Xeon CPU

P6 Microarchitecture Core.
Dynamic Execution: multiple branch prediction, dataflow analysis,
speculative execution.
MMX.

PSE36 addressing mode (part of Intel's Extended Server Memory Architecture):
up to 64 Gbyte of addressable main memory.

Level 1 cache: 16 kbyte instruction, 16 kbyte data (Harvard architecture),
non-blocking.
Level 2 cache: 512 kbyte or 1/2 Mbyte, 4-way set-associative, non-blocking,
BSRAM.
The level 2 cache runs at the same speed as the processor core, like at the
Intel Pentium Pro CPU.
ECC (Error Correcting Code).

Multi-processor support (4-CPU with 450NX chipset, 8-CPU (announced: fourth
quarter 1998): Saber architecture, Corollary Profusion chipset).

At the introduction, a bug in 4-CPU 450NX chipset based systems was
discovered, which delayed the introduction of these systems.

Management functions accessible through SMBus:
ROM containing type and stepping data, thermal information,
additional information can be added by OEM,
temperature sensor.

100/400 MHz: 512 kbyte or 1 Mbyte L2 cache, June 1998, 30.8 W.
100/450 MHz (announced: September 1998): 512 kbyte or 1/2 Mbyte L2 cache,
38.1 W.
100/500 MHz (announced: begin 1999).

2.0 V, 3.3 V I/O.

Package: 330 pin SEC module (Single Edge Contact) (Slot 2).

Technology: 5 layer metal, 0.25 micron CMOS.
7.5E6 transitors in core.
Die size: 130.9 mm2.

Deschutes.


2.56.6 Intel Katmai CPU

Intel Pentium II CPU with KNI instruction set (Katmai New Instructions).

100/450 MHz.
100/500 MHz.

Announced: first quarter 1999.

Package: Slot 1.

Technology: 5 layer metal, 0.25 micron CMOS,
later 0.18 micron (second half 1999).

Plans for mobile version canceled in May 1998.


2.56.7 Intel announcements

Mobile Celeron for low-cost notebooks (announced: first quarter 1999),
366 and 400 MHz (announced: end 1999).

Dixon: mobile Mendocino with 256 kbyte on-chip level 2 cache for low-cost
notebooks,
266 MHz (announced: fourth quarter 1998),
333 MHz (announced: first half 1999), 366 MHz (announced: end 1999).

Dual-processor modules for Slot 2 systems (DP Ready, Camino chipset).

Willamette: successor Intel Pentium II CPU series,
600 MHz (announced: end 1999), 0.18 micron, later 0.13 micron.

Coppermine: mobile version of Willamette, 100/450 and 100/500 MHz,
AC/DC powering (Geyserville technology), 0.18 micron technology,
announced: end 1999.

Tanner: Xeon with KNI, 100/500 MHz (announced: first quarter 1999),
multi-processor support (4-CPU: Lion32 architecture),
Slot 2 and Slot M, technology: 0.25 micron.

Cascades: Xeon with KNI, 700 MHz (announced: second half 1999),
technology: 0.18 micron.

P7, Merced: 64 bit architecture (IA-64),
EPIC (Explicit Parallel Instruction Computing, narrow VLIW
(Very Long Instruction Word)),
multi-processor support (4-CPU with 460GX chipset: Lion64
architecture),
600 MHz, 133 MHz external bus,
Slot M (64/128 bits),
announced: mid 2000,
14E6 transistors, die size: 300 mm2, technology: 0.18 micron,
800 MHz, copper,
successor (2002): 0.13 micron.

Intel will introduce copper chips only in 2001, together with the 0.13 micron
technology.


2.57 AMD K6 CPU

Pentium Pro class CPU with MMX technology.
Based on the NexGen Nx686 CPU design.
Intel Pentium/MMX P55C CPU pin compatible.

Dual processor support.

Optimized for 16 bit code.

Superscalar: 6-stage, 7 execution units: load, store, 2 integer, FPU, branch,
MMX.
Features: X86 to RISC86 instruction translation, instruction predecoding,
out-of-order execution, speculative execution,
central Instruction Control Unit.
Branch prediction: 8192-entry branche history table,
16-entry BTB (Branch Target Buffer),
16-entry return address stack.

32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Instruction cache: 2-way set-associative, 32 bytes per line,
single cycle access.
Data cache: write-back, 2-way set-associative, 32 bytes per line,
simultanious load and store in single cycle, MESI architecture.

Model 6.

66/166 MHz (PR166): 2.9 V core, 3.3 V I/O, April 1997.
60/180 MHz: 2.9 V.
66/200 MHz (PR200): 2.9 V core, 3.3 V I/O, April 1997.
66/233 MHz (PR233): 3.3/3.2 V core, 3.3 V I/O, April 1997.

Technology: 5-layer metal, 0.35 micron C4 CMOS.
8.8E6 transistors, from which 3E6 for the cache.
Die size: 162 mm2.

Model 7.

66/233 MHz: January 1998.
66/266 MHz: January 1998.
66/300 MHz: April 1998.

2.2 V core, 3.3 V I/O.

Technology: 0.25 micron CMOS.
8.8E6 transistors, from which 3E6 for the cache.
Die size: 68 mm2.

Package: 321 pin PGA (Pin Grid Array) (Socket 7).

100/300 MHz.
100/350 MHz (announced: third quarter 1998).
100/400 MHz (announced: fourth quarter 1998).

2.2 V core, 3.3 V I/O.

Package: 321 pin PGA (Pin Grid Array) (Socket 7+).


2.57.1 AMD K6-2 CPU

3DNow! technology: 3D multi-media instruction set (21 instructions).

Two MMX execution units.

Model 8.

66/266 MHz: May 1998.
95/333 MHz: May 1998.
100/300 MHz.
100/350 MHz (announced: third quarter 1998): Socket 7+.
100/400 MHz (announced: fourth quarter 1998): Socket 7+.

2.2 V core, 3.3 V I/O.

Package: 321 pin CPGA (Ceramic Pin Grid Array) (Socket 7).

Technology: 5 layer metal, 0.25 micron CMOS.
9.3E6 transistors.
Die size: 68 mm2.

K6-3D, Chompers.

Model 9: 256 kbyte level 2 cache.

100/350 MHz (announced: fourth quarter 1998).
100/400 MHz (announced: fourth quarter 1998).

2.2 V core, 3.3 V I/O.

Technology: 0.25 micron CMOS.
9.3E6 transistors.
Die size: 135 mm2.

Sharptooth.


2.57.2 AMD announcements

K6-3 (Sharptooth): K6-2 with on-chip level 2 cache.

K7: announced: begin 1999,
Slot A (Intel Slot 1 compatible) or EV6 (DEC Alpha CPU compatible).

Copper technology: announced: end 1999, new fab in Dresden, Germany.
1 GHz K7 in 2000.


2.58 IBM 6x86MX CPU

Cyrix 6x86MX CPU.


2.59 Cyrix 6x86MX CPU

Pentium Pro class CPU with MMX technology.
Intel Pentium/MMX P55C CPU pin compatible.

64 kbyte unified cache: 4-way set-associative, 32 bytes per line.
256 byte instruction line cache: 8-entry, fully-associative,
32 bytes per line.

Superscalar: register renaming, out-of-order execution, speculative execution.
Branch prediction: 512-entry branch target cache, 4-way set-associative,
1024-entry branch history cache.
TLB (Translation Look-aside Buffer): 16-entry L1, direct mapped, dual-ported,
384-entry L2, direct mapped, dual-ported.

Optimized for 32 bit code.

66/133 MHz (Cyrix 6x86MX-PR166+ CPU): May 1997.
66/166 MHz (Cyrix 6x86MX-PR200+ CPU).
75/188 MHz (Cyrix 6x86MX-PR233+ CPU).
66/200 MHz.

The multiplier can be 2, 2.5, 3, or 3.5.

Dual voltage: 2.8 V core, 3.3 V I/O.

83/208 MHz (Cyrix 6x86MX-PR266 CPU): March 1998, 2.9 V core, 3.3 V I/O.
75/225 MHz (Cyrix 6x86MX-PR300 CPU): April 1998, 0.25 micron IBM CMOS.
100/250 MHz (Cyrix 6x86MX-PR333 CPU): announced: third quarter 1998.

Package: 296 pin PGA (Pin Grid Array) (P54C socket compatible).

Technology: 5-layer metal, 0.35 micron CMOS (IBM and SGS-Thomson).
6E6 transistors.
Die size: 194 mm2.

M2.


2.59.1 Cyrix announcements

Cayenne: announced: 1998,
own 3D multi-media instruction set.


2.60 Centaur IDT WinChip C6 CPU

Intel Pentium/MMX P55C CPU compatible.

Cache: 32 kbyte data, 32 kbyte instruction.

50/150 MHz: 3.3 V, never produced.
60/180 MHz.
66/200 MHz.
75/225 MHz.

3.3 or 3.52 V.

Package: 296 pin PGA (Pin Grid Array) (Socket 7).

Technology: 0.35 micron CMOS.
5.4E6 transistors.
Die size: 88 mm2.


2.60.1 Centaur IDT WinChip C6+ CPU

53 additional "X86" instructions.

Announced: second half 1998.

83/266 MHz: 3.3 V.
100/300 MHz: 2.5 V.

Technology: 0.35 micron CMOS.
5.8E6 transistors.
Die size: 91 mm2.

100/300 MHz.

Technology: 0.25 micron CMOS.
5.8E6 transistors.

Package: 296 pin PGA (Pin Grid Array) (Socket 7+).


2.60.2 Centaur IDT WinChip-2-3D C6+ CPU

WinChip C6+ with 3DNow! technology.

66/266 MHz (announced: second half 1998).
100/300 MHz (announced: second half 1998).

Technology: 0.35 micron CMOS.

100/300 MHz (announced: fourth quarter 1998).

Technology: 0.25 micron CMOS.

Package: 296 pin PGA (Pin Grid Array) (Socket 7+).


2.61 Multi-Media CPU

2.61.1 Cyrix MediaGX CPU

The Cyrix MediaGX CPU together with the MediaGX Cx5510 companion chip
implements a complete PC system including 64 bit FPM / EDO DRAM controller
(maximum 128 Mbyte in 4 banks), ISA and PCI bus, video and audio.

Core:
superscalar,

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