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C64 interrupts question

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Ian Kenny

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Apr 29, 2004, 6:17:18 PM4/29/04
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Hi, is there any info somewhere on the C64 interrupts? I'd like to know
which parts of the C64's operation were dealt with by interrupts. For
example, what caused the CPU to start its interrupt routines? Particular
keys, signals from the clock? etc.

Cheers


White Flame (aka David Holz)

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Apr 29, 2004, 9:02:41 PM4/29/04
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"Ian Kenny" <Ian....@btinternet.com> wrote in message
news:16fkc.847$7S2.168@newsfe1-win...

This information is gleaned from the Programmer's Reference Guide, Mapping
the C64, and 64doc.txt.

Every 1/60th of a second (even on PAL machines), Timer A in CIA#1 triggers
an IRQ, which scans the keyboard, blinks the cursor, and handles such KERNAL
things.

Tape I/O uses both CIA#1 timers and triggers IRQs.

Serial bus I/O uses Timer A in CIA#1 to trigger IRQs for its timing.

RS232 routines use both CIA#2 timers during sends & receives to trigger an
NMI per bit.

The Restore key is directly tied (through some debouncing circuitry) to the
NMI line, and isn't part of the normal keyboard scanning.

The VIC-II chip can trigger IRQs based on raster line, sprite-sprite
collision, sprite-background collision, or light pen position, none of which
are enabled in default operation.

CIA#1's interrupt line is tied to /IRQ, CIA#2's interrupt line is tied to
/NMI. CIAs can interrupt based on timer underflow, the (unused) CNT/SP
serial port, time-of-day alarm, or an external pin. The KERNAL only uses
the timers, as described above.

/IRQ and /NMI are also exposed on the expansion (cartridge) port.


General interrupt info:

The CPU has 2 pins on it, called /IRQ and /NMI. These are tied to +5V
through a pull-up resistor, and when something wants to activate an
interrupt, it grounds one of those lines to 0V. When the VIC-II or CIA
flags an interrupt, it holds the line low until you acknowledge it by
reading/writing to the interrupt registers of those chips. If multiple
chips are holding the line low, the CPU can't tell; it must poll the chips
to see which one(s) are triggering the interrupt condition.

Interrupts wait until the current instruction is finished before the
trigger, but if there are 2 or less cycles remaining in the current
instruction, it will run the next one as well before handling the interrupt.
When the interrupt occurs, the program counter and processor flags are
pushed to the stack, and the Interrupt Disable flag is set. When the
interrupt exits, it resumes operation at the previous PC and restores the
processor flags (which include the previous Interrupt Disable flag state).

An IRQ is triggered only if the Interrupt Disable bit (I) of the CPU is
cleared, and the /IRQ line is active. If /IRQ is held low, IRQs will
continuously trigger immediately when the Interrupt Disable bit is cleared.

A NMI is triggered only on the falling edge of the /NMI line, and cannot be
ignored. If the NMI line is held low, no NMIs are triggered until it's
released to +5V and brought back to ground. So, if you set CIA#2 to trip a
NMI and never acknowledge it, NMI will be held low and no other NMI sources
will be detected (including the Restore key).

--
White Flame (aka David Holz)
http://www.white-flame.com/
(spamblock in effect)


Sam Gillett

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Apr 29, 2004, 10:14:18 PM4/29/04
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"Ian Kenny" <Ian....@btinternet.com> wrote ...

I think you can find an eText version of the C64 Programmers Reference Guide
on Project 64.

http://project64.c64.org/index.htm

It should answer most of your questions.

--
Best regards,

Sam Gillett

Change is inevitable,
except from vending machines!


Arkmay

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Apr 29, 2004, 11:34:06 PM4/29/04
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"Ian Kenny" <Ian....@btinternet.com> wrote in message news:<16fkc.847$7S2.168@newsfe1-win>...

At the beginning of each interrupt the computer gets the start address
of the service-routine out of the addresses $0314 and $0315.
The SEI and CLI instructions set or clear the interrupt enable bit.
That's so you can change the IRQ vector to point to some other
routine.
Interrupts can come from peripherals like graphics chip, serial port,
keyboard, etc. or the built in timers or sound chips. There is also a
non-maskable interrupt (cant be disabled).
Try this Programmers Reference Guide, that's what I use.
http://www.c64.priv.no/c64/files/books_prg_C64_Programmers_Reference_Guide.txt

Ian Kenny

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Apr 30, 2004, 4:20:42 PM4/30/04
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Thanks guys. That's really helpful.

"Arkmay" <markm...@hotmail.com> wrote in message
news:765a0d92.04042...@posting.google.com...

Christian Johansson

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May 1, 2004, 3:01:59 AM5/1/04
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> Try this Programmers Reference Guide, that's what I use.
>
http://www.c64.priv.no/c64/files/books_prg_C64_Programmers_Reference_Guide.txt

Here is an HTML version of the Programmer's Reference Guide. I think that is
much better than a .txt. version:

http://www.devili.iki.fi/Computers/Commodore/C64/Programmers_Reference/front_cover.html


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