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deciphering how arm assembly code uses condition codes
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Bernard Talbert
May 6, 2012, 6:36:22 PM5/6/12
to
Need some help decipher some ARM assembly code that doesn't have
comments.
Some of the instructions use conditional execution and I'm trying to
figure out higher level
"if condition" they are checking for. For example in the following
snippet
the ANDS is setting condition codes. What "if equal" condition is the
BEQ instruction
checking for here? Equal to what? If the instruction setting
conditions codes were CMP
I know its (x == y) where x and y are the operands. But what is for
ANDS here?
rsb r3, r0, #0 /* r3 = -r0 */
ands r3, r3, #0x1C /* r3 = (r3 & 0x1c), setCPSR.flags(r3) */
beq 3f /* if (equal?) goto 3f */
I'm having trouble decipher the following also. The MOVS sets
condition codes.
What condition are the store byte instructions checking for? CS = HS
right?
So greater-than or equal to what?
movs r12, r3, lsl #31 /* r12 = (r3 << 31), set
CPSR.flags(r12) */
strcsb r1, [r0], #1 /* if ?(C==1) *(r0) = r1, r0 += 1 */
strcsb r1, [r0], #1 /* if ?(C==1) *(r0) = r1, r0 += 1 */
strmib r1, [r0], #1 /* if ?(N==1) *(r0) = r1, r0 += 1 */
comments.
Some of the instructions use conditional execution and I'm trying to
figure out higher level
"if condition" they are checking for. For example in the following
snippet
the ANDS is setting condition codes. What "if equal" condition is the
BEQ instruction
checking for here? Equal to what? If the instruction setting
conditions codes were CMP
I know its (x == y) where x and y are the operands. But what is for
ANDS here?
rsb r3, r0, #0 /* r3 = -r0 */
ands r3, r3, #0x1C /* r3 = (r3 & 0x1c), setCPSR.flags(r3) */
beq 3f /* if (equal?) goto 3f */
I'm having trouble decipher the following also. The MOVS sets
condition codes.
What condition are the store byte instructions checking for? CS = HS
right?
So greater-than or equal to what?
movs r12, r3, lsl #31 /* r12 = (r3 << 31), set
CPSR.flags(r12) */
strcsb r1, [r0], #1 /* if ?(C==1) *(r0) = r1, r0 += 1 */
strcsb r1, [r0], #1 /* if ?(C==1) *(r0) = r1, r0 += 1 */
strmib r1, [r0], #1 /* if ?(N==1) *(r0) = r1, r0 += 1 */
Boudewijn Dijkstra
May 7, 2012, 5:17:17 AM5/7/12
to
Op Mon, 07 May 2012 00:36:22 +0200 schreef Bernard Talbert
<bernard...@gmail.com>:
Conditional Execution, you would have found out that EQ means "if Z==1".
Predictably, ANDS sets Z when the result is zero.
> Equal to what?
The term "equal" only makes sense when you perform a compare operation.
> If the instruction setting conditions codes were CMP
> I know its (x == y) where x and y are the operands. But what is for
> ANDS here?
>
> rsb r3, r0, #0 /* r3 = -r0 */
> ands r3, r3, #0x1C /* r3 = (r3 & 0x1c), setCPSR.flags(r3) */
> beq 3f /* if (equal?) goto 3f */
>
> I'm having trouble decipher the following also. The MOVS sets
> condition codes.
> What condition are the store byte instructions checking for? CS = HS
> right?
As the pseudocode definition says, LSL sets C equal to the last bit
shifted out and N to the MSB of the result.
> So greater-than or equal to what?
Also this term only makes sense when you perform a compare operation.
> movs r12, r3, lsl #31 /* r12 = (r3 << 31), set
> CPSR.flags(r12) */
> strcsb r1, [r0], #1 /* if ?(C==1) *(r0) = r1, r0 += 1 */
> strcsb r1, [r0], #1 /* if ?(C==1) *(r0) = r1, r0 += 1 */
> strmib r1, [r0], #1 /* if ?(N==1) *(r0) = r1, r0 += 1 */
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Gemaakt met Opera's revolutionaire e-mailprogramma:
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<bernard...@gmail.com>:
> Need some help decipher some ARM assembly code that doesn't have
> comments.
>
> Some of the instructions use conditional execution and I'm trying to
> figure out higher level
> "if condition" they are checking for. For example in the following
> snippet
> the ANDS is setting condition codes. What "if equal" condition is the
> BEQ instruction checking for here?
If you had read the section in the Architecture Reference Manual about
> comments.
>
> Some of the instructions use conditional execution and I'm trying to
> figure out higher level
> "if condition" they are checking for. For example in the following
> snippet
> the ANDS is setting condition codes. What "if equal" condition is the
> BEQ instruction checking for here?
Conditional Execution, you would have found out that EQ means "if Z==1".
Predictably, ANDS sets Z when the result is zero.
> Equal to what?
The term "equal" only makes sense when you perform a compare operation.
> If the instruction setting conditions codes were CMP
> I know its (x == y) where x and y are the operands. But what is for
> ANDS here?
>
> rsb r3, r0, #0 /* r3 = -r0 */
> ands r3, r3, #0x1C /* r3 = (r3 & 0x1c), setCPSR.flags(r3) */
> beq 3f /* if (equal?) goto 3f */
>
> I'm having trouble decipher the following also. The MOVS sets
> condition codes.
> What condition are the store byte instructions checking for? CS = HS
> right?
shifted out and N to the MSB of the result.
> So greater-than or equal to what?
> movs r12, r3, lsl #31 /* r12 = (r3 << 31), set
> CPSR.flags(r12) */
> strcsb r1, [r0], #1 /* if ?(C==1) *(r0) = r1, r0 += 1 */
> strcsb r1, [r0], #1 /* if ?(C==1) *(r0) = r1, r0 += 1 */
> strmib r1, [r0], #1 /* if ?(N==1) *(r0) = r1, r0 += 1 */
Gemaakt met Opera's revolutionaire e-mailprogramma:
http://www.opera.com/mail/
(Remove the obvious prefix to reply privately.)
druck
May 7, 2012, 5:40:17 AM5/7/12
to
On 6 May 2012 Bernard Talbert <bernard...@gmail.com> wrote:
> Need some help decipher some ARM assembly code that doesn't have
> comments.
Try the ARM Architecture Reference Manual. There are ones for each
> Need some help decipher some ARM assembly code that doesn't have
> comments.
Architecture version, but the one here covers the basics of arithmetic
instructions and condition codes.
http://www.scss.tcd.ie/~waldroj/3d1/arm_arm.pdf
---druck
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Bernard Talbert
May 7, 2012, 2:27:55 PM5/7/12
to
On May 7, 2:17 am, "Boudewijn Dijkstra" <sp4mtr4p.boudew...@indes.com>
wrote:
book.
That's how I added those pseudocode comments using the manual. ;-)
But you answered my question. I forgot EQ checks for Z=1 and the AND
could
produce zero result. Got it!!
> As the pseudocode definition says, LSL sets C equal to the last bit
> shifted out and N to the MSB of the result.
I also forgot carry flag is set from result of barrel shift. Got it.
thanks
wrote:
> Op Mon, 07 May 2012 00:36:22 +0200 schreef Bernard Talbert
> <bernard.talb...@gmail.com>:
>
> If you had read the section in the Architecture Reference Manual about
> Conditional Execution, you would have found out that EQ means "if Z==1".
> Predictably, ANDS sets Z when the result is zero.
I did read that manual. I also have ARM System Developer's Guide
> If you had read the section in the Architecture Reference Manual about
> Conditional Execution, you would have found out that EQ means "if Z==1".
> Predictably, ANDS sets Z when the result is zero.
book.
That's how I added those pseudocode comments using the manual. ;-)
But you answered my question. I forgot EQ checks for Z=1 and the AND
could
produce zero result. Got it!!
> As the pseudocode definition says, LSL sets C equal to the last bit
> shifted out and N to the MSB of the result.
thanks
ddawg...@gmail.com
Jun 25, 2016, 12:35:16 PM6/25/16
to
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