14mhz '816 from Sanyo
Jerry Chang
Sorry guys, I missed the original post about the subject. I can't find it.
Read through about 200 mesg. trying to find it.
Sounds like it is physically the same as the WDC '816s. Except this one runs
at 14mhz and still draws 5V, right? If I want to upgrade my twgs ( with 32k ),
I just have to get a 56mhz oscillator for it; at least technically, huh?
Thanx for any info.
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< Jerry Chang | Terripin Transit - Berkeley, CA >
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Soenke Behrens
>Sounds like it is physically the same as the WDC '816s. Except this one runs
>at 14mhz and still draws 5V, right? If I want to upgrade my twgs ( with 32k)
>I just have to get a 56mhz oscillator for it; at least technically, huh?
Well, it's not "physically the same" (else it would not be faster :), indeed,
it looks very different ... on the inside, that is. The pinout and packaging
is just its old grubby self.
To upgrade to 14 MHz, you'd need a 56MHz oscillator, and, depending on
your TWGS, a cache upgrade. Let's see .. 14 MHz, that means 35 ns. If you
have that or slightly faster SRAM, it should work. Also, be sure you have the
new PALs that can go to 15 MHz. Ah, of course you'll have to swap the CPU :)
Soenke
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Jawaid Bazyar
>Sorry guys, I missed the original post about the subject. I can't find it.
>Read through about 200 mesg. trying to find it.
>Sounds like it is physically the same as the WDC '816s. Except this one runs
>at 14mhz and still draws 5V, right? If I want to upgrade my twgs ( with 32k ),
>I just have to get a 56mhz oscillator for it; at least technically, huh?
You need to make sure your cache chips are fast enough for 12-14MHz. I
believe 35ns will do.
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Jerry Chang
Welp, the 32k cache seems to have 35ns cache SRAM. I guess it is sufficient.
Will it help if I put 25ns ( maybe 15ns ) SRAM on it?
Jerry Chang
Welp, my twgs got the 32k cache ( 35ns ). But I am not sure about the PALs.
How do I tell if I have it?
Thanx.
Kim Brennan
> To upgrade to 14 MHz, you'd need a 56MHz oscillator, and, depending on
> your TWGS, a cache upgrade. Let's see .. 14 MHz, that means 35 ns. If you
> have that or slightly faster SRAM, it should work. Also, be sure you have the
> new PALs that can go to 15 MHz. Ah, of course you'll have to swap the CPU :)
Hmmm, this is the first I've heard about 'new' PALs on the TWGS. Do you know
how to tell which PALs are which? Since I've got BOTH a TWGS and a Zip, I'd
like to be able to upgrade both at some point.
-=> Message from Kim Brennan <=-
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Marc Sira
> > To upgrade to 14 MHz, you'd need a 56MHz oscillator, and, depending on
> > your TWGS, a cache upgrade. Let's see .. 14 MHz, that means 35 ns. If you
> > have that or slightly faster SRAM, it should work. Also, be sure you have t
>
What's the procedure for determining minimum memory speed from clock speed?
Like, Soenke got 35ns from 14MHz above...how?
And what does PAL stand for (and what do they do)?
Are there no PALs on a ZIP? (the custom ASIC takes care of it?)
Why do I know what TWGS, SRAM, and ASIC stand for, but not PAL? B-)
Thanks...
Marc Sira | "Zyblor is our leader..."
t...@micor.ocunix.on.ca | "Zyblor is all-knowing..."
'
Chris Deschu
I called AE about this (I work for an authorized dealer), and the
tech I spoke with told me that the GAL's they currently have are only rated
at 11mhz... where did someone hear of some that would do 15? The part number
he gave me was 10MHZPALKIT. I have my TWGS running at 8.5mhz now, with all
stock parts (except the crystal), and the CPU has a -7 on it... is 14mhz
pushing these new chips to the limit, or is it possible to do 15 or so?
BTW, the retail price of that kit is $79.00, I'm glad I work for a dealer :)
That plus $95 for the new CPU, plus $79 for the 32k cache upgrade, is
basically doubling the price of the TransWarp... Good luck all!
Chris Deschu
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tuu
In article <905TNB...@micor.ocunix.on.ca> t...@micor.ocunix.on.ca (Marc Sira) writes:
}What's the procedure for determining minimum memory speed from clock speed?
}Like, Soenke got 35ns from 14MHz above...how?
The memory has to be able to respond in one clock cycle..
Thus 1/14000000 = 71nanoseconds.
You have to know specifically that the 6502 family chips (inc. 65816)
require memory at twice the main clock speed as memory is only accessed
during half of the clock cycle. So divide 71 by 2, and you get approx 35.
}And what does PAL stand for (and what do they do)?
Programmed Array Logic.. The outputs are a function of the inputs.
That is, they can do what would otherwise require a *lot* of simple gate
chips [ands/ors/etc] can do in one chip. They are programmed at a high
level, and, at least when I used them a few years ago, the source went
through a few stages before it was at the level to be programmed onto the
chip. [There were optimization stages, to make sure it would all fit on the
chip, etc]
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Anthony J. Stuckey
>> > From: behr...@Informatik.TU-Muenchen.DE (Soenke Behrens)
>> > To upgrade to 14 MHz, you'd need a 56MHz oscillator, and, depending on
>> > your TWGS, a cache upgrade. Let's see .. 14 MHz, that means 35 ns. If you
>> > have that or slightly faster SRAM, it should work. Also, be sure you have t
>> > new PALs that can go to 15 MHz. Ah, of course you'll have to swap the CPU :
>>
>Everything I ever wanted to know and, apparently, am not afraid to ask:
>What's the procedure for determining minimum memory speed from clock speed?
>Like, Soenke got 35ns from 14MHz above...how?
1000 ns == 1 MHz.
8 MHz -> 125 ns (1/n type thing...)
14 MHz -> 70 ns, but I've heard many many times that there's something
truly wierd in the IIs that requires the clock speed to be effectively
doubled when doing this division. I know that My Laser manual states 150 ns
memory will not work in 3.6 MHz mode (7.2 x 150 > 1000).
>And what does PAL stand for (and what do they do)?
Programmed Array Logic. similar to an eprom.
>Are there no PALs on a ZIP? (the custom ASIC takes care of it?)
no clue.
>Why do I know what TWGS, SRAM, and ASIC stand for, but not PAL? B-)
haphazard experience??
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Scott Alfter
> 14 MHz -> 70 ns, but I've heard many many times that there's something
>truly wierd in the IIs that requires the clock speed to be effectively
>doubled when doing this division. I know that My Laser manual states 150 ns
The "weirdness" is that CPU and video accesses to memory are
interleaved. The IIe tech ref explains the process in more detail.
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David....@bbs.actrix.gen.nz
> In article <BrCCK...@news.cso.uiuc.edu> stu...@mrcnext.cso.uiuc.edu (Anthony J. Stuckey) writes:
> > 14 MHz -> 70 ns, but I've heard many many times that there's something
> >truly wierd in the IIs that requires the clock speed to be effectively
> >doubled when doing this division. I know that My Laser manual states 150 ns
>
> The "weirdness" is that CPU and video accesses to memory are
> interleaved. The IIe tech ref explains the process in more detail.
Nope, that only applies to the "slow" RAM (1 MHz), and it is more an
effect than a cause.
"Double speed" RAM is required is because the 6502 and derivatives only
use the second half of each clock cycle to access memory. The CPU
provides a stable address half way through the cycle and the data read
or write is completed at the end of the cycle. The RAM is effectively
being accessed at twice the CPU clock speed, so you need RAM with half
the expected access time.
Since the first half of each cycle is essentially free, Woz decided to
"borrow" it to perform video accesses. It also avoided having to
implement dynamic RAM refreshing, which is done automatically as a side
effect of the video accesses.
The "fast" RAM is basically idle for the first half of each clock
cycle. Since there are no video accesses, the fast RAM needs to be
refreshed. This is done by the FPI chip (Fast Processor Interface),
and is the reason why the IIgs actually runs at about 2.6 MHz despite
having a 2.8 MHz CPU clock speed - the slow-down is due to memory
cycles being "stolen" from the CPU to do memory refreshing.
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