On Tuesday, 15 January 2013 07:29:29 UTC+10, Alex Freed wrote:
> You bet. I did run the soft 6502 at 25 MHz. There is also enough fast
>
> memory on the CB to shadow the whole A2 memory space. The problem is
>
> that to write data back to the main on-board memory or the memory space
>
> on the slot cards it will still take slowing down to 1 MHz.
The Zip Chip does this (or appears to) by queueing memory writes to a FIFO. The FIFO can presumably write a byte to the bus on every cycle. Since the Zip is aware of the MMU configuration at any point in time, it's able to (presumably) pause itself when the memory configuration changes and flush the write queue.
Slowing down is therefore only necessary on a cache miss, MMU state change, or when an IO range marked as 'slow' is hit. I expect the 'slowdown' is reset by a 50-100ms timer.
You could do this on a Carte Blanche, which would effectively be a Transwarp II functional clone. It would be very interesting to know at what speed the memory bandwidth became a limiting factor. Certainly more than the 8-10 Mhz of the Zip/Rocket chips. Probably less than 25 :-)
Matt