I have not tried using HDV images with the Mister Apple II core because so much of what I would want to use disk-writing for would be in DOS 3.3.
You asked "What FPGA is used in the Mister?"
The Mister is built around the DE10-nano, which, in turn, is built around the Intel Cyclone V SE FPGA. From the Terasic (the manufacturer of the DE10-nano) Internet site:
FPGA Device
Intel Cyclone® V SE 5CSEBA6U23I7 device (110K LEs)
Serial configuration device – EPCS64 (revision B2 or later)
USB-Blaster II onboard for programming; JTAG Mode
HDMI TX, compatible with DVI 1.0 and HDCP v1.4
2 push-buttons
4 slide switches
8 green user LEDs
Three 50MHz clock sources from the clock generator
Two 40-pin expansion headers
One Arduino expansion header (Uno R3 compatibility), can be connected with Arduino shields
One 10-pin Analog input expansion header (shared with Arduino Analog input)
A/D converter, 4-pin SPI interface with FPGA
* If the specification of memory device in Quick Start Guide and official website is discordant, refer to DE10-Nano website as the sole stardard.
HPS (Hard Processor System)
800MHz Dual-core ARM Cortex-A9 processor
1GB DDR3 SDRAM (32-bit data bus)
1 Gigabit Ethernet PHY with RJ45 connector
USB OTG Port, USB Micro-AB connector
Micro SD card socket
Accelerometer (I2C interface + interrupt)
UART to USB, USB Mini-B connector
Warm reset button and cold reset button
One user button and one user LED
LTC 2x7 expansion header