Z80 its refresh pin
srk...@gmail.com
Im putting together a Z80 clone card for the Apple II (softcard copy),
but have have come across some unusual behaviour of my Z80 that im not
familiar with (its a NEC D780C) - and that is, it asserts its refresh
pin low (28), and keeps it there?? (right after reset - I need it high
to boot). Ive read the data sheet, and acordingly this refresh is a
state machine thats controlled by the R register that simply times its
self from the clock pin (6)
Any idea's on why this could be happening??
thanks,
Steve
Patrick Schaefer
> Im putting together a Z80 clone card for the Apple II (softcard copy),
> but have have come across some unusual behaviour of my Z80 that im not
> familiar with (its a NEC D780C) - and that is, it asserts its refresh
> pin low (28), and keeps it there??
The D780C should behave exactly like a Z80 -- I have a few Softcard
clones that use this CPU. So try another one, your may have gotten ESD
damage.
Patrick
Steven Hirsch
At the risk of stating the obvious: Have you verified that the Z80 is actually
getting a clock signal?
srk...@gmail.com
My D780C works fine in my softcard, so it does work correctly. I have
two chips that I try just as a sanity check. Both behave the same -
both refresh low, all other signals good, so its definately my design.
Its just that I have no idea why it behaves this way. My test
equipment tells me the CPU is receiving a nice 2.040MHZ Clock (the C
can handle up to 4MHZ i think). The design is an identical copy of
microsoft's (with a few FPGA implementation tweaks), so i expect it is
a timing issue. Without knowing what could invoke the Z80 into this
state makes it hard to begin looking for it.
thanks for the responses.
Steve.
zwsd...@gmail.com
> microsoft's (with a few FPGA implementation tweaks), so i expect it is
> a timing issue. Without knowing what could invoke the Z80 into this
> state makes it hard to begin looking for it.
Is the CPU actually executing? Trigger on falling edge of _M1 and
verify that you see the correct waveform (_M1 and _RFSH should be out
of phase within the instruction fetch portion of the instruction
cycle).
Is _BUSRQ externally asserted? That will take the Z80 off-bus
permanently and float _RFSH.
And for the obvious one... Are you sure that the Z80 is actually
asserting _RFSH and it's not something else on your PCB... isolate
that pin of the chip, put a pullup on it, and see what it's doing.
srk...@gmail.com
>
> Is the CPU actually executing? Trigger on falling edge of _M1 and
> verify that you see the correct waveform (_M1 and _RFSH should be out
> of phase within the instruction fetch portion of the instruction
> cycle).
I havent triggered off M1 yet, Im just plugging into to this now. Ive
been working on the vital signs, and with the softcard design, the
refresh pin is part of the combinational logic that enables external
address and data drivers during phase 0, so ill have to connect in
before these to see if I can see it cycling trying to load at add
0x00. The Z80 is a new processor to me, so its a bit of a learning
curve. Do you know exactly what the Z80 does when it comes out of
reset?
>
> Is _BUSRQ externally asserted? That will take the Z80 off-bus
> permanently and float _RFSH.
Yep. BUSRQ is firmly high - i drive it from a totempole output, (in
my last test, I connected it to 5V0 direct, but still refresh sets low
and stays there) I have also checked to make sure WAIT is set high
and HALT responds with a high,which they do.
>
> And for the obvious one... Are you sure that the Z80 is actually
> asserting _RFSH and it's not something else on your PCB... isolate
> that pin of the chip, put a pullup on it, and see what it's doing.
Ive removed all connections to refresh, then pulled refresh high via a
1k resistor to 5V0 - the Z80 still pulled this thing low (down to .9v
from 5V0).
Crazy. Im sure its going to be something simple. My next step is to
replace the clock with something else. Its the only thing that seems
to govern refresh. My current clock is not exactly a 50/50 duty cycle.
steve
Patrick Schaefer
> My current clock is not exactly a 50/50 duty cycle.
That seems not to be critical. The Microsoft Softcard operates a 4MHz
Z80 with bursts of 3,58MHz: 2 cycles there, 2 missing, 2 there, 2
missing. That's far from 50/50.
Patrick
zwsd...@gmail.com
> before these to see if I can see it cycling trying to load at add
> 0x00. The Z80 is a new processor to me, so its a bit of a learning
> curve. Do you know exactly what the Z80 does when it comes out of
> reset?
I haven't had to debug it to this level; I actually never used DRAM in
a Z80 design. I was lazy :)
If you can't get past this problem I will bring a Z80 board into work
(my scope here has deeper memory than my home scopes) and capture A0,
A1, M1, RFSH triggering on rising edge of RESET, so maybe we can see
something of interest.
> replace the clock with something else. Its the only thing that seems
> to govern refresh. My current clock is not exactly a 50/50 duty cycle.
As long as you're not violating the rise/fall time ratings, this
wouldn't be the issue, I've clocked it off 25% duty cycle without
problems. The Z80 is a fully static processor.
Alex Freed
few mysteries around it. The refresh wire goes active (low)for the 2
last clocks on an instruction fetch (M1) cycle.
Two things may be relevant here:
1. The clock has to go nearly all the way up to 5V. Not good driving it
with TTL chips. Use a pull-up transistor as in the SoftCard or better a
CMOS buffer.
2. SoftCard has to use a very special clocking scheme to be able to
access the Apple's memory transparently. It pulses twice during PH0 and
stays low during PH1. Well documented.
-Alex.
srk...@gmail.com
>
> Two things may be relevant here:
> 1. The clock has to go nearly all the way up to 5V. Not good driving it
> with TTL chips. Use a pull-up transistor as in the SoftCard or better a
> CMOS buffer.
Ah, I hope this could well be the problem. Although it looks great on
the CRO, it only peaks at about 4.2V (due to the translators, as im
executing off a real chip for the moment). I might try putting a
120ohm pull up on the clock pin to see if that helps, otherwise an
inline sot-23 buff should do the trick. I didnt realise the clock was
so sensitive on the Z80's.
>
> 2. SoftCard has to use a very special clocking scheme to be able to
> access the Apple's memory transparently. It pulses twice during PH0 and
> stays low during PH1. Well documented.
I think i might have this bit ok. An image of the captured FPGA wave
form shows it seems to look the part;
http://users.tpg.com.au/srkh//PH0%2BPH1%2BPIN6.png
dang REFRESH is still low!..
thanks,
Steve
.
David Wilson
> > 2. SoftCard has to use a very special clocking scheme to be able to
> > access the Apple's memory transparently. It pulses twice during PH0 and
> > stays low during PH1. Well documented.
>
> I think i might have this bit ok. An image of the captured FPGA wave
> form shows it seems to look the part;
>
> http://users.tpg.com.au/srkh//PH0%2BPH1%2BPIN6.png
Unless my eyes deceive me, you have the double pulse during PH1 rather
than PH0.
Alex Freed
This is correct. I wrote from (bad) memory. PH1 is the CPU access time.
-Alex.
Alex Freed
>> than PH0.
>>
>
> This is correct. I wrote from (bad) memory. PH1 is the CPU access time.
What I mean is PH1 high is the time when the clock actually toggles. It
stays low during all of PH0 and as a result the address and data lines
do not change during the time when PH0 is high so that is a good time to
read/write the memory on the motherboard.
Back to the original topic. Z80 is a relatively simple CPU. Only the
clock is needed to check it. Pull the data lines down to 0 with say 1K
resistors and the IRQ, NMI, WAIT, RESET and DREQ lines up and it should
start counting up on the address lines and properly driving the MREQ,
RD, M1 and RFSH lines. The 0x00 is a NOP instruction so it will execute
it forever.
-Alex.