ASIC Chip
Andy Stein
Many of you have heard about the ASIC 65C816 chip, which was supposed
to accelerate the Apple IIGS to 21 MHz. I have heard that with the Zip
GSX, tests showed it to only operate at 9.5 MHz. You can already get a Zip
GSX running at 10 MHz, so it doesn't seem like much of an advantage. I
hope they fix it so it runs at 21 MHz.
Jawaid Bazyar
That was with a Transwarp GS.
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Tim Meekins
It's really up in the air how fast it will end up. It's very dependent on
what is used to contruct the chip and who does it. The current fabricator
ran tests on the chip and said it will run at 17 MHz. Once this chip
is being produced, it won't be very hard to reach the gola of 25 Mhz.
There are several large companies who I may not be allowed to reveal who
are testing the chip and making some nice suggestions for the chip.
TIM MEEKINS Ask me about GNO! - MultiTasking on a IIGS!
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Stephen Brown
[cut]
>
>People, please don't bother to post stuff like this unless you have more
>details. MY information has it that the prototypes were in silicon and
>running at 17 mhz -- this was in a test bed, not a GS system. To date I
>know of one running successfully in a 7 mhz TWGS; Tim and Jawaid can
>probably tell us more about that.
>
>Todd Whitesel
>toddpw @ tybalt.caltech.edu
The differences between the ASIC 65816 and WDC 65816 centre around the
implementation (or non-implementation) of the ABORT' pin. Is this used in the
TWGS or in the ZIP? Perhaps I should get to my point: Established that the
ASIC chip is compatible with the TWGS, is it compatible with the ZIP?
Also, given that prototypes exist, are devices on the market yet, and if not,
when are they expected to be?
[btw: Apple II forever!]
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Todd P. Whitesel
>The differences between the ASIC 65816 and WDC 65816 centre around the
>implementation (or non-implementation) of the ABORT' pin.
Au contraire. The central difference is that the WDC version is an ick
design that was laid out on a kitchen table, and the ASIC uses real
CAD design tools. It is a lot easier for the ASIC folks to get their
chip to run faster, whereas WDC has pretty much maxed out at 10-12 (barely)
and they cannot do better without laying out the chip again using a scheme
similar to what the ASIC dudes are doing. WDC's main market (controllers)
does not require hideous speed, so it is not a priority for them.
Eric Mcgillicuddy
That has nothing to do with the ABORT pin not being implemented. It might have
something to do with speed, but this too I doubt, the rated speed of a 17MHz
ASIC is about 12MHz. Most manufacturers derate their products 30% for
reliability reasons.
The only place the GS uses the ABORT pin is the memory expansion card. I do
not know what it is used for, DMA maybe? It may have no effect of operation,
or it may mean that ASIC can't be fully GS compatible. I don't know.
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Todd P. Whitesel
>That has nothing to do with the ABORT pin not being implemented. It might have
>something to do with speed, but this too I doubt, the rated speed of a 17MHz
>ASIC is about 12MHz. Most manufacturers derate their products 30% for
>reliability reasons.
It has everything to do with speed. WDC's design has little analog gotchas
most of the time running at any speed higher than 4 mhz -- which is why
Apple won't buy large quantities of faster chips from them. Specifically,
there's a timing constraint such that the last cycle of a REP or SEP
instruction _must_ be 250 ns long because it depends on a signal propagating
through a wire that runs all the way across the die. (This is from memory
so I am probably off by a bit, but this is the essential problem.) The
early TWGS boards had to insert extra delays in artificially in order to
make things work. Unless WDC has fixed this it would also help to explain
why Zip is so religous about hand-picking the CPUs that they use.
>The only place the GS uses the ABORT pin is the memory expansion card. I do
>not know what it is used for, DMA maybe? It may have no effect of operation,
>or it may mean that ASIC can't be fully GS compatible. I don't know.
Currently it is not used for anything. It is on the memory expansion slot
for future expansion (perhaps Apple thought somebody could make a VM system
of some kind with it).
What I want to know is just what sort of "broken" is the WDC ABORT pin?
Does it at least do what it says in the data sheet?
Roy Bannon
>for future expansion (perhaps Apple thought somebody could make a VM system
>of some kind with it).
>What I want to know is just what sort of "broken" is the WDC ABORT pin?
>Does it at least do what it says in the data sheet?
Well, my MMU used the ABORT pin. It worked almost like they say in the
data sheet for my application. However, it does have a problem. The
data sheet says (I think) that on an abort, it save the address of the
opcode which got aborted. What it really save is the pc when the abort
occured. This is different. For example LDA #$7fffff is to be aborted
because 7ffffff is not a to be accessed by the current process. The
pc that gets pushed on the stack is pointing to the FF, not to the LDA.
So when the abort routine looks at the stack, it can't figure out what the
opcode was and where to return to. My mmu is going to latch opcode fetch
address (lower bits) so it the abort routine can figure it out.
Roy
ban...@sono.uucp
Jawaid Bazyar
>That has nothing to do with the ABORT pin not being implemented. It might have
>something to do with speed, but this too I doubt, the rated speed of a 17MHz
>ASIC is about 12MHz. Most manufacturers derate their products 30% for
>reliability reasons.
>The only place the GS uses the ABORT pin is the memory expansion card. I do
>not know what it is used for, DMA maybe? It may have no effect of operation,
>or it may mean that ASIC can't be fully GS compatible. I don't know.
What I'd like to know is, who says the ABORT pin isn't implemented in
the ASIC? The ABORT signal is used for virtual memory, which is why it
appears on the RAM expansion slot, but it's not used in the IIgs for any reason
whatsoever.
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Todd P. Whitesel
>data sheet says (I think) that on an abort, it save the address of the
>opcode which got aborted. What it really save is the pc when the abort
>occured.
Yep, that's definitely broken. You're right about the data sheet, and there
should be a latch inside the CPU remembering the PC every instruction fetch
for ABORT handling.