On Friday, 8 May 2020 10:48:13 UTC+10, Kent Dickey wrote:
> Great information!
Indeed, thanks for all the great docs, Antoine.
> It also implies that the Apple IIc, with the IWM, has a 65c02 without
> the false-reads.
I don't think this is the case, but I'll try to test it later today.
As Tom said, this is well documented by Sather (as I posted above).
If true then a //e enhancement kit would fail with RWTS.
The terminology is confusing. There are invalid and multiple accesses.
The 65C02 removes all (?) invalid (reads) and some multiple accesses.
STA (zp),Y became a single write, which fixes the POKE problem.
But STA abs,X still has the read then write, to work with RWTS.
The cycle count is the same - for the same reason.
Here's what Sather said on page 4-26:
"From this induced idle state,
the software can syne itself to the logic sequencer
with the statement, "STA $C08F,X". This instruction
performs a double access to $COEF (assuming
Slot 6). The first access is decoded in the disk controller
to cause the logic state sequencer to leave its
idle state and begin its write loop. The second access
stores actual disk write data in the controller's input/
output register. The controller will only accept data
on the clockpulse after the one which started the
logic state sequencer and on every fourth clockpulse
afterward. The writing technique involves writing
data in software loops that take exact multiples of
four cycles to execute.
Persons wishing to imitate the writing technique
of the RWTS subroutine should not substitute a
"STA $COEF" instruction for the "STA $C08F,X" at
address $B83F of DOS 3.3, "STA $COEF" will start
up the software loop one clockpulse out of sync with
the logic state sequencer, and the controller won't
accept the write data. "STA $COEF,X" will work
with 0 in the X-register. The instruction must make
a double access to $COEF."
What's surprising is that he missed some things though...
On page 4-25 he wrote:
"* Statements marked by an asterisk in this application note are
true for the 6502 but not the 65C02."
But at the end of the previous quote from 4-26
"Another address mode of
instruction which will work is a STA (ZP),Y with no
This should have an asterisk if his 65C02 changes are correct.
It won't work on a 65C02.