GS memory expansion timing

[woodsworth1]

Is there some place where I can find information about the iigs memory expansion connector - in particular timing diagrams and the way address signals are multiplexed to create the FRA9..0 signals for at /CRAS and /CCAS?

Its something missing from the hardware manual

thanks.

[Antoine Vignau]

Hi,
Does pages 157+ of http://www.brutaldeluxe.fr/documentation/cortland/v3_01_CortlandHardwareReference.pdf help?
--
Antoine

[woodsworth1]

On Monday, April 24, 2023 at 5:33:06 AM UTC+10, Antoine Vignau wrote:
> Does pages 157+ of http://www.brutaldeluxe.fr/documentation/cortland/v3_01_CortlandHardwareReference.pdf help?

It doesn't. Thanks for the reference but it contains less information than the GS hardware reference although a couple of differences in the description. Also it indicates that the 14M signal is on memory the expansion connector when it is not (just phi2).

Anyway what I wanted to know is when in the phi2 cycle the 24 bit address is "known" to the exapnasion card. That would be when FRA9..0 in RAS and/or CAS have all of the low address bits. (the bank is on the data bus on the phi2 rising edge and A15..10 are valid at that time too). If I was doing it I would put A9..0 on FRA9..0 when they are valid (rising edge of phi2) and use them for the RAS address, and change to upper address/bank for CAS. That way the ROM address would not need to change giving maximum timie for a slow ROM to get its data out. But its not my design, so...

So I had a look at the signals on a DSO. As I suspecdted the phi2 (2.8MHz) clock is asymmetrical. Its derived from the 14M clock, but 2.8 = 14 / 5, which doesn't divide nicely, so the phi2 clock is low for two 14M cycles (about 140ns) and high for three 14M cycles (about 210ns) unless it is extended (for MEGA2 access synchronised to its 1MHz clock) when it could be high for quite a few 14M clock cycles.

The FPI chip seems to watch both edges of the 14M clock. I noticed that there are repetitive refresh cycles going to the memory expansion connector. These occur about every 3.5us, one going to each bank successively then repeating (that is the CROW<x> signals change for each refresh). The refresh is a CAS-before-RAS refresh cycle with the CAS being asserted for the entire high period of the phi2 clock (didn't see one happen while the phi2 cycle was being extended, though I didn't look for it) and the RAS being asserted a little later.

unfortuantely the FPI doesn't assert the CCAS and CRAS signals when not accessing the memory expansion so I need to figure an easy way of reading thos signals without wrecking a RAM card that I want to keep. The iie technical reference has pseudo timing diagrams and specifies the signals on hte multiplexed RAM address bus so I don't see why apple didn't make that available for the GS

[fadden]

You may want to ask on https://retrocomputing.stackexchange.com/. I've seen a little relevant traffic there, e.g. https://retrocomputing.stackexchange.com/q/10884/56, though that was talking about ROM access rather than RAM.

[woodsworth1]

On Tuesday, April 25, 2023 at 1:16:29 AM UTC+10, fadden wrote:
> You may want to ask on https://retrocomputing.stackexchange.com/. I've seen a little relevant traffic there, e.g. https://retrocomputing.stackexchange.com/q/10884/56, though that was talking about ROM access rather than RAM.

I looked, thank-you. Some related stuff but not what i was looking for.

So I sacrificed an old 256K (only) Apple branded GS memory card which I'm not sure if it worked anyway, and checked out the signals myself.

The falling edge of RAS during a memory expansion access cycle coincides with the rising edge of phi2. it is held low for three 14M cycles (about 210ns). In a read access the CAS is asserted 70ns later (one 14M cycle) and is released when RAS is also released (140ns), In a write access the CAS is asserted 35ns later than for a read (ie one and a half 14M clock cycles after RAS) and is still released when RAS is (105ns duration).

The signals are as follows (sorry about formatting):
RAS CAS [falling edges]
FRA0 A0 B0
FRA1 A1 A9 (MSEL= Hi) or B2 (MSEL = Low)
FRA2 A2 A10
FRA3 A3 A11
FRA4 A4 A12
FRA5 A5 A13
FRA6 A6 A14
FRA7 A7 A15
FRA8 A8 B1
FRA9 A9 A9 (MSEL = Hi) or B3 (MSEL = Low)

CROW<x> are B2 & B3 (MSEL = Hi) or B4 and B5 (MSEL = Low)

All bank signals are available on the data pin on the rising edge of Phi2.
The corollory is that on the rising edge of Phi2 the entire 24-bit address can be determined by the memory expansion card and that's what I wanted to know.

thanks everyone