Questions about Amiga, IBM, Mac buses (updated)
Richard Akerman
Here is what I know, please fill in the blanks and elaborate (Dave Haynie?)
IBM
---
Speed (MHz) Width (bits) Address Space (MB) transfer speed
ISA 8 16 ? 8 MB/s
EISA 8.33 32 ? 32 MB/s
Micro Channel 10 32 ? 40 MB/s
VESA (VL-Bus) same as CPU 32 ? 132 MB/s
external clock
PCI same as CPU 32/64 ? ?
external clock
PCMCIA card ? ? ? ?
Notes:
ISA - Industry Standard Architecture
EISA - Extended ISA
VESA - Video Electronics Standards Association
PCI - Peripheral Component Interconnect
PCMCIA - Personal um somethingorother
ISA, EISA and MicroChannel all have to communicate through bus arbitration
hardware.
VL-Bus is processor-direct. "The VL-Bus standard covers only CPUs running at
clock rates of up to 40 MHz. ... At clock speeds higher than 40 MHz, system
makers must buffer the signals so that they don't overload the CPU ... At 50
MHz and above, VL-Bus systems are also limited to one VL-Bus slot to reduce
the demand on the CPU. A forthcoming _mezzanine_ version of VL-Bus, which
will add support for a 64-bit data path, promises to separate the electronics
of the local bus from the CPU. This will allow for more peripherals to sit on
the local bus without introducing wait states or overloading the CPU." (quote
from _PC/Computing_ March '93, p. 103)
PCI is a proposed standard from Intel. It is also a "local-bus" design like
VL-Bus. However, "...it supports _multimaster concurrency_. That means that
several peripherals on the PCI bus can act as masters simultaneously,
communicating with one another while the central processor is tied up with
other instructions. ... Another theoretical PCI bus advantage is its support
for burst-mode reads and writes." (quote from _PC/Computing_ March '93, p.
110)
different PCMCIA standard levels?
Mac
---
Speed (MHz) Width (bits) Address Space (MB) transfer speed
NuBus 10 16/32 ? ? ?
PDS ? ? ? ?
Notes:
PDS - Processor Direct Slot
burst mode?
multiple bus masters?
autoconfiguring capability?
PDS varies depending on machine?
Amiga
-----
Speed (MHz) Width (bits) Address Space (MB) transfer speed
Zorro II 7.09-7.16* 16 8 ?
Zorro III 25** 32 ? ?
ISA 8 16 ? 8 MB/s?
CPU slot ? ? ? ?
Video slot ? ? ? ?
PCMCIA card ? 16? ? ?
Notes:
* "there are two [clock signals], 90 degrees apart" (from Dave Haynie)
** Zorro III is 25 MHz when clocked by the A3000/A4000 bus master, but other
bus masters could drive it faster (from Dave Haynie)
Why is it called Zorro?
AUTOCONFIG (tm) provides automatic configuration
burst mode?
multiple bus masters?
different CPU slots in A2000, A3000, A4000?
different Video slots in A2000, A3000, A4000?
different PCMCIA standard levels? Amiga is level II (16 bits, I/O)?
If Zorro-II cards are used in Zorro-III slots, can the use the larger address
space? For example, my GVP Series II can have up to 8 MB in 2 MB blocks, but
is currently limited to 6 MB because my AT BridgeBoard needs 512K of
AUTOCONFIG space. Could I have 8 MB on the GVP and an AT BB on a Zorro-III
bus?
Dave Haynie
theoretical max
Speed (MHz) Width (bits) Address Space (MB) transfer speed
>
>ISA 8 16 16MB* 8 MB/s
>EISA 8.33 32 4GB* 32 MB/s
>Micro Channel 10 32 4GB* 40 MB/s
>
>VESA (VL-Bus) same as CPU 32 4GB* 132 MB/s
> external clock
>
PCI same as CPU 32/64 4GB* 100-260MB/s
> external clock
*Some notes on these for those who care. The Intel-inspired buses, as well as
supporting some maximum address space (as indicated), also support an "I/O"
address space, which varies in size. PCI supports a 4GB I/O space, and a
"configuration" space which is a small area of standard registers per device
(a little like the Amiga's autoconfig space, only it doesn't go away after a
device is configured).
It's not correct to call these "IBM" buses -- IBM doesn't use EISA or VESA,
while some non-Intel systems use ISA, EISA, and PCI. The best description I
have for them is "Intel Inspired". ISA and VESA are pretty much based directly
on the Intel CPU local bus protocols of their generation, with some additions
based on standard IBM-PC hardware. EISA is of course an upgrade of ISA.
MicroChannel is very Intel-centric. ISA is a bit more CPU independent, but it
does consider everything necessary to support oddities of Intel CPUs, like
"I/O Space", that aren't too common on other CPUs anymore.
>PCI is a proposed standard from Intel. It is also a "local-bus" design like
>VL-Bus.
PCI is really a replacement for a local bus. It's what I call an interchip bus.
In the first half of the 80s, you really needed only one kind of bus in a PC,
the CPU's local bus. Sure you had expansion buses, but they weren't much beyond
buffered versions of the local bus, probably with a few extensions for I/O card
management. Everything from the Apple II bus to the ISA bus to the Zorro II
bus fall in this category. Eventually you got machines that still supported
such expansion buses but no longer had the original CPU bus to drive them. The
'386 based PCs and A2500s are examples of these.
Once a CPU was going faster and no longer tied to the design of the
expansion bus, it became clear that the local and expansion bus designs
would be two different things. A local bus would have to change with the
CPU, while the expansion bus would have to stay standard for years. This
led to improved expansion buses at least functionally independent of any
CPU local bus (Zorro III, EISA, MCA). Of course, now that these weren't
directly related to the local bus, folks found some things couldn't be done
on them that could be done on the local bus. Like our CPU slot (well, we
had them since '86, but few others had expandable local buses). The PC
folks all started out with proprietary local buses, mainly for DRAM, which
had to be fast. Ultimately, they came around to looking for a standard for
this too. Now, the driving force for this, from a systems house view,
was "fast local bus cards". Intel's approach, which is a viewpoint I
starting taking shortly after the A3000 project, is that the main point of
the local bus is chip to chip interconnect. More often you're seeing CPUs
that provide a fast bus optimized for cache and/or DRAM, and a local bus
for "everything else". That's basically what PCI is for.
>However, "...it supports _multimaster concurrency_. That means that several
>peripherals on the PCI bus can act as masters simultaneously, communicating
>with one another while the central processor is tied up with other
>instructions. ...
What that really means is that any bus master that wants cycles asks for them.
The bus is centrally arbitrated, and the CPU is just another master asking or
not asking for cycles. Any backplane bus, such as NuBus or FutureBus, has to
deal with the same concept (though FutureBus is actually done via distributed
rather than central arbitration). So if the CPU is off doing something else,
other bus masters will get the bus. Even if it isn't, the arbiter is supposed
to round robin the bus. In fact, Intel spends lots of concern for bus latency
and other issues of concern to realtime systems, though surprisingly, they
don't have support for split transactions on PCI.
theoretical max
> Speed (MHz) Width (bits) Address Space (MB) transfer speed
>
>NuBus 10 16/32 4GB 33MB/s
>PDS ? ? ? ?
There are a couple of different Apple PDS slots. The one that's on the 25MHz
68030 systems would max out at 80MB/s, like the 25MHz '030 bus itself. That's
using burst, it's more like 50MB/s without burst.
>Amiga
theoretical max
> Speed (MHz) Width (bits) Address Space (MB) transfer speed
>
>Zorro II 7.09-7.16* 16 16 ~3.5MB/s
>Zorro III N/A 32 4GB 100MB/s+
>CPU slot 16,25MHz 32 4GB 80MB/s
(A3k/A4k)
>Video slot N/A 13(A2k,A3k) N/A N/A
25(A4k)
The Zorro II bus itself can address 16MB. The various limits (8.5 MB on A2000,
10MB on A3000/A4000) are system-imposed, not a restriction of Zorro II.
The A3000/A4000 acting as a Zorro III bus master derives its timing from two
25MHz clocks set 90 degrees apart. The theoretical maximum speed of this
bus bridge is about 33MB/s, but that's not in any way related to Zorro III
itself, it's a detail of the current bus bridge implementation.
>Why is it called Zorro?
Way back in the old days, various Amiga motherboards had code names. One was
"Lorraine", one was "Zorro". When Bill Kolb did up the expansion specs, he
did them for the Zorro prototype, so the schematics said "Zorro" on them.
Everyone started calling the bus Zorro, so we kept that for the 32-bit version.
>burst mode?
Zorro III has a burst protocol, the CPU slot uses the 68030 bus conventions for
burst. Zorro II has no burst mode.
>multiple bus masters?
The Zorro II and Zorro III buses support multiple bus masters.
>different CPU slots in A2000, A3000, A4000?
The A2000 has a 16/24-bit slot based on the 68000 local bus. The A3000 and
A4000 have a 32/32-bit slot based on the 68030 local bus. The A4000 slot is
a superset of the A3000 slot (a few signals have been added to support the
use of non-CPU things on the slot, but so far nothing takes advantage of these).
>different Video slots in A2000, A3000, A4000?
The A2000 and A3000 have the same video slot specification. The A4000 provides
a superset of this with 25-bit pixel data (rather than 13), a hardware blanking
indicator, and a pixel-synchronous clock.
>If Zorro-II cards are used in Zorro-III slots, can they use the larger address
>space?
No, a Zorro II card can only address 24-bits worth of space. It is true that
we opened up some extra Autoconfig space for Zorro II cards in all Zorro III
implementations (though I still don't think the OS is using it), but a Zorro II
card is physically limited to the original 16MB of Zorro II space.
--
Dave Haynie / Commodore Technology, High-End Amiga Systems Design (cool stuff)
"The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh BIX: hazy
"Head like hole, black as your soul, I'd rather die than give you control" -NIN