MarkYoungIW <
MarkY...@yahoo.com> wrote:
> 7F8 Even!!
Aha, found it. In the SetFIQ macro (see Macros.s)
https://www.riscosopen.org/viewer/view/castle/RiscOS/Sources/Networking/Econet/s/Macros?rev=4.4
the macro uses MRS and MSR instructions to switch into FIQ32 mode - because
ARM6 and later has two kinds of FIQ mode, 26 and 32 bit mode. RISC OS
normally runs in 26 bit user/supervisor mode, but uses 32 bit mode for FIQs.
ARM2 doesn't have any 32 bit modes, or MRS/MSR intructions, which is why
it's falling over.
This is the code:
212: [ {TRUE} ; ; Cope with
32bit CPUs
213: MRS $regc, CPSR ; Switch to
_32 mode with IRQs and FIQs off
214: ORR $regb, $regc, #I32_bit :OR: F32_bit ; Has to be
done in two stages because RISC OS
215: MSR CPSR_cxsf, $regb ; can't
return to a 32bit mode and interrupts
216: ORR $regb, $regb, #2_10000 ; can occur
after the MSR but before the following
217: MSR CPSR_cxsf, $regb ;
instruction.
218: ]
219: ADR $rega, FIQVector
220: LDR $regb, =&E51FF004 ; LDR pc, .+4
= LDR pc, [ pc, #-4 ]
221: STR $regb, [ $rega ], #4
222: [ {TRUE} ; ; Cope with
32bit CPUs
223: ; And switch back
224: MSR CPSR_cxsf, $regc
225: ]
226: [ StrongARM
227: ; Local version of OS_SynchroniseCodeAreas, because it's far too
much hassle
228: ; calling a SWI in these circumstances
229: MRC ARM_config_cp, 0, $regc, ARM_ID_reg, C0, 0
230: AND $regc,$regc,#&F000
231: TEQS $regc,#&A000
232: BNE %FT01 ; not StrongARM
233: ; We want to clean the (32-byte) data cache line containing
234: ; the FIQVector word.
235: ADR $regc, FIQVector
236: MCR ARM_config_cp, 0, $regc, ARM8A_cache_reg, C10, 1 ; clean DC
entry
237: MCR ARM_config_cp, 0, $regc, ARM8A_cache_reg, C10, 4 ; drain WB
238: MCR ARM_config_cp, 0, $regc, ARM8A_cache_reg, C5, 0 ; flush IC
239: ; Normally 4 NOPs could be required to make sure the
240: ; modified instruction wasn't in the pipeline. Fortunately
241: ; we know that the FIQ vector can't be called within 3
242: ; instructions of here (and if an FIQ were to go off, the
243: ; pipeline would be flushed anyway).
244: 1
245: [ ARM810support
246: SUB PC,PC,#4 ; flushes branch predict on ARM810 (local
equivalent of OS_SynchroniseCodeAreas)
247: ]
248: ]
First, you don't need lines 226-248, so you can NOP those out (replace each
instruction with MOV r0,r0 so the length is the same). I think you'll get
the StrongARM code, but not the ARM810.
Now, lines 213-217 set svc32 mode with IRQs and FIQs off. I think this will
work as a replacement to turn off IRQs and FIQs (since ARM2 doesn't have a
svc32 mode, only svc mode):
MOV $regc, pc
ORR $regb, $regc, #(1<<26) OR (1<<27)
TEQP $regb, #0
then lines 219-221, then replace 222-225 with:
TEQP $regc, pc
(replacing spare instructions with MOV r0,r0)
This is where it gets messy. You'll need to replace every instance of
SetFIQ with the same code. I've written the above in macro form, because
each macro instance may use different registers. Note that it's invoked in
other source files too, like Background.s
I /think/ that should be it (ie there's no other MSR/MRS instructions in
Macros. But I may well have missed something.
Theo