RTflow is a dataflow modeling tool for real-time systems design; a
free, lightweight counterpart to expensive, heavyweight tools like
MathWorks Simulink, National Instruments LabVIEW and SystemBuild. In
RTflow, the model is built in a graphical block schematics language,
and the tool features a graphical simulator for efficient verification
and bug-finding. It generates implementation code for both software (C/
C++/Java) and FPGA (synthesizable VHDL). To the best of my knowledge,
it is the first free tool in the world that offers code generation for
both software and FPGA from the same model, hence allowing the user to
postpone the decision of what hardware to implement on. You can read
more about RTflow and download it at http://www.rtflow.com .
RTflow is a joint project between me personally, DST Control AB in
Sweden and the Alexandra Institute A/S in Denmark.
Regards,
Jerker Hammarberg