generate HDL code for flip flops

Andrea

unread,

Dec 14, 2010, 4:31:04 AM12/14/10

to

Dear all,
I'm new to Simulink, I hope you can help me.
I want to generate a flip flop D HDL code using Simulink HDL coder.
When I try to generate it for the existing flip flop (D or JK) in Simulink Library, several errors occurred:

1. The trigger port of a triggered subsystem must have a boolean or ufix1 type
2. Output port 'Q' must have 'Output when disabled' set to 'held' for HDL code generation
3. Output port '!Q' must have 'Output when disabled' set to 'held' for HDL code generation
4. Output port '!Q' must have an initial value of 0 for HDL code generation
5. The trigger port of a triggered subsystem must have a boolean or ufix1 type
6. Output port 'Q' must have 'Output when disabled' set to 'held' for HDL code generation
7. Output port '!Q' must have 'Output when disabled' set to 'held' for HDL code generation

I've the last Matlab version 2010b
Thanks in advance

Tim McBrayer

unread,

Dec 17, 2010, 2:00:54 PM12/17/10

to

Andrea wrote:
> Dear all,
> I'm new to Simulink, I hope you can help me.
> I want to generate a flip flop D HDL code using Simulink HDL coder.
> When I try to generate it for the existing flip flop (D or JK) in
> Simulink Library, several errors occurred:

If you want a standard D flip flop, use a Unit Delay block. Simulink HDL Coder also
supports options for controlling reset and enable styles.

Regards,
--
Tim McBrayer
The MathWorks

Andrea

unread,

Dec 21, 2010, 3:19:32 AM12/21/10

to

Tim McBrayer <Tim.Mc...@mathworks.com> wrote in message <iegc16$6r4$1...@fred.mathworks.com>...

Thanks a lot for the advice, I did as you said and my system works! :)
I have another problem now: how can I do to display the reset, enable and clock signals that HDL coder produces? I need to visualize them on my Simulink schematic
Thanks a lot for the support.

Tim McBrayer

unread,

Dec 22, 2010, 4:48:39 PM12/22/10

to

Hardware-specific artifacts such as the clock, enable and reset signals are not part of
the original Simulink model and cannot be displayed in the block diagram. Simulink HDL
Coder is not intended to operate as a schematic design entry tool. Hardware-specific
features such as the control signals you mention are not modeled explicitly in Simulink,
but are inferred from the Simulink simulation semantics and generated into the HDL output.
This lets you worry about modeling a solution to your problem, without having to worry
about low-level details such as clock routing.

Regards,
--
Tim McBrayer
MathWorks

Stanislav

unread,

Mar 28, 2011, 2:17:41 PM3/28/11

to

What if enable signals required for multicycle system? I try to use Sample&Hold block from DSP blockset, but generated HDL looks very strange and slow. Is there any "design pattern" to implement clock enable (for later use with "Multicycle Enable" constraint in Xilinx UCF file)?

Tim McBrayer

unread,

Mar 30, 2011, 1:52:35 PM3/30/11

to

Stanislav wrote:
> What if enable signals required for multicycle system? I try to use Sample&Hold block from DSP blockset, but generated HDL looks very strange and slow. Is there any "design pattern" to implement clock enable (for later use with "Multicycle Enable" constraint in Xilinx UCF file)?
>

Simulink HDL Coder supports code generation for multirate Simulink models. It generates a
local multirate design, which has a single clock input running at the fastest rate in the
design. Slower rates in the design have their clocking signals created by an
automatically generated timing controller. For more details see "Generating HDL Code for
Multirate Models" in the Simulink HDL Coder User Guide. The tool can also optionally
generate multicycle path information. While this information is in a generic format, it
is formatted to allow easy conversion to Xilinx UCF format, or to any other synthesis
tool's file format. This process is also documented in the User Guide section I mentioned
above.