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rename simulink signals

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rofl

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Feb 10, 2015, 8:04:14 AM2/10/15
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I want to explicitly rename a simulink signal without getting a 'Signal label mismatch' from diagnostics. I don't want to switch the diagnostic off in general, but am looking for an explicit way of telling simulink, that here a name change should take place, but without using blocks that have other semantics (like a gain) or cause signal copies (non-virtual blocks).
This is necessary in several circumstances:
- the context changes, e.g. i have an input preprocessing block that feeds from input driver blocks with topological signal names. If the signal doesn't need any reformattings I still need to rename it to it's functional name (say Input_board5_Pin6 to TractionInterlock2) for further use in the application context.
- A library block has a named ouput signal that is (naturally) rather abstract (e.g. sig_filt) but outside the lib block I want to give it a more specific name (e.g. battery_current_filt).
- with a gateway functionality I need to rename a bus signal from the source network name to the destination network name.
I created a masked library block with "RENAME" on it that simply routes the signal through, but still got the mentionioned diagnostic warning because library blocks aren't exempted from the test.
I inserted a vector concatenation block with a single input, even though I wasn't really happy with an additional block inside the lib. That worked fine for non-busses, but with a bus signal I got really weird behaiviour. While a bus selector connected to the output still would show all named bus-signals, when initialising the model an error is thrown saying the respective signal could not be found in the bus.
So is there any clean way of renaming a signal in simulink?

Kyle

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May 28, 2015, 1:41:00 PM5/28/15
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I am having the same issue with library blocks

John Harris

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Nov 2, 2016, 12:24:10 PM11/2/16
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I have the same kind of problem...for example I have a generic model which will be referenced by another model.

My generic referenced model has two inputs which may be driven by the same source signal, or by separate signals.

I/O ports are named within the domain of the system, so the root level of a referenced model is going to have one signal name (controlPwr) while its source signal in the top level model will have another name (mainBatteryBus).

John Harris

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Nov 2, 2016, 4:36:16 PM11/2/16
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It looks like Signal Conversion block is what's designed for this purpose.
Nothing in the Signal Conversion dialog or help page says anything about signal labels, but it seems to be what it's designed for.
If you know different, let me know.
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