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x86 Reordering
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Horizon68
Jul 15, 2019, 1:43:02 PM7/15/19
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Hello..
x86 Reordering
All modern x86 chips from Intel and AMD aggressively reorder
instructions across a window which is around 200 instructions deep on
recent CPUs from both manufacturers (i.e. a new instruction may execute
while an older instruction more than 200 instructions "in the past" is
still waiting). This is generally all invisible to a single thread since
the CPU still maintains the illusion of serial execution by the current
thread by respecting dependencies, so from the point of view of the
current thread of execution it is as-if the instructions were executed
serially.
So i think the memory barriers positions of my scalable MLock (that is a
scalable lock) are ok, read about it here:
https://sites.google.com/site/scalable68/scalable-mlock
Thank you,
Amine Moulay Ramdane.
x86 Reordering
All modern x86 chips from Intel and AMD aggressively reorder
instructions across a window which is around 200 instructions deep on
recent CPUs from both manufacturers (i.e. a new instruction may execute
while an older instruction more than 200 instructions "in the past" is
still waiting). This is generally all invisible to a single thread since
the CPU still maintains the illusion of serial execution by the current
thread by respecting dependencies, so from the point of view of the
current thread of execution it is as-if the instructions were executed
serially.
So i think the memory barriers positions of my scalable MLock (that is a
scalable lock) are ok, read about it here:
https://sites.google.com/site/scalable68/scalable-mlock
Thank you,
Amine Moulay Ramdane.
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