cacheDisable not flushing L2 cache, PPC750
---
Can anyone tell me how cacheDisable(DATA_CACHE) behaves with respect to L2
cache? I am suspecting (and have reason to believe, below) that it only
flushes, invalidates, and disables the L1 cache.
Our board uses a PPC750 processor and has 1MB external L2. Hardware maps
0x2000000-0x2fffffff (0x2-space) as a non-cache alias of 0x0-space.
We also program the MMU (either BATs or PTEs if we're using a page table)
WIMG bits as follows:
0x0-space: 0010 (memory-coherent)
0x2-space: 0100 (inhibit-cache)
If I write to a 0x2-space address, it goes right to main memory. If I write
to 0x0-space, and caching is enabled, it won't go out to main memory until
its associated cache line is evicted. There is no special external snooping
that forces a flush of 0x0-space when 0x2-space is accessed. So, if I read
the contexts of a 0x0-space address, and compare that to the contents of its
0x2-space alias, they may not necessarily be the same if caching is enabled.
If caching is disabled (and the cache is properly flushed), the contents
should be the same.
So I wrote a simple little test to verify this:
void
flushVerify()
{
for (int* i=0; i < (int*)0x10000000; ++i)
{
int valZeroSpace = *i;
int valTwoSpace = *(i+0x8000000);
if (valZeroSpace != valTwoSpace)
printf("bad flush -- addr: 0x%x, 0x%x != 0x%x\n",
i, valZeroSpace, valTwoSpace);
}
}
void
cacheTest()
{
// It isn't clear whether cacheDisable flushes just the L1 cache, or
both
// L1 and L2. Try it.
cacheDisable(DATA_CACHE);
// verify the flush
flushVerify();
}
If I do not enable L1 and L2 data caches at startup (can control via boot
flags), then the test above works fine (i.e., 0x0- and 0x2-space are
coherent). If I do enable both caches however, the test fails. It finds
several places where the two spaces do not agree.
Any thoughts?
Thanks in advance,
--Michael
Jay
> Greetings,
>
> Can anyone tell me how cacheDisable(DATA_CACHE) behaves with respect to L2
> cache? I am suspecting (and have reason to believe, below) that it only
> flushes, invalidates, and disables the L1 cache.
>
If you have L2 cache then you are responsible for writing drivers for that.
Michael Carr
"Jay" <jayesh.sa...@honeywell.com> wrote in message
news:d029b3aa.04011...@posting.google.com...
> <---> wrote in message news:<100g0l4...@corp.supernews.com>...
> > Greetings,
> >
> > Can anyone tell me how cacheDisable(DATA_CACHE) behaves with respect to
L2
> > cache? I am suspecting (and have reason to believe, below) that it only
> > flushes, invalidates, and disables the L1 cache.
> >
> vxWorks does not support L2 cache. cacheDisable() only works for L1
cache.
> If you have L2 cache then you are responsible for writing drivers for
that.
Okay -- next obvious question: does anyone have the algorithm for flushing
and disabling (atomically) the PPC750 L1 and L2 caches? I've tried writing
one that does starts with cacheDisable (flush and disable L1 flash),
followed by simple displacement flushing (i.e., reads from text space, every
32 bytes), L2E clearing, and flash invalidation of L2, with interrupts
disabled. But as soon as a re-enable interrupts, all hell breaks loose (the
runnign task get s confused about tis stack or data on it), which implies to
me the disaplacement flush did not clear out everything.
Thoughts? My implementation is below, comments welcomed.
Thanks in advance,
--Michael
#define _ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
.globl FUNC(l2CacheDisable)
.text
.align 2
/*
void l2CacheDisable(void* start, size_t len)
Displacement flush the L2 cache (i.e., push out old dirty lines by pulling
in new clean lines). Then, disable the cache and invalidate all cache
lines.
r3: start address of clean region
r4: length of region to walk through
Currently assumes two-way set associative, 1MB cache,
4 32-byte sectors per tag line.
*/
l2CacheDisable:
/* disable interrupts and translation (keep original msr in r0 for later)
*/
mfmsr r0
lis r5,-1
ori r5,r5,0x7fef /* clear EE and DR bits)
and r5,r0,r5
mtmsr r5
isync
/* r3 will be cursor, and r4 will be highAddr */
add r4,r3,r4
/* do a displacement flush by walking through a read-only region,
one L1 cache block at a time */
2:
cmplw cr1,r3,r4
beq cr1,3f
lbz r5,0(r3)
addi r3,r3,0x20 /* advance an L1 cache line */
b 2b
/* flush complete, now disable the cache */
3:
sync
isync
li r7,0
mtspr 1017,r7
sync
isync
/* now do a global invalidate and wait for it to finish */
oris r7,r7,0x0020
mtspr 1017,r7
sync
isync
4:
mfspr r7,1017
andi. r7,r7,1 /* poll for L2IP to clear */
isync
bne 4b
/* restore original EE and DR bits */
5:
li r7,0
mtspr 1017,r7
isync
mfmsr r5
andi. r0,r0,0x8010
or r5,r5,r0
mtmsr r5
isync
blr
D.
---
should by nature include the running task's entries.
Thanks
"D." <dolis...@yahoo.com> wrote in message
news:LoyOb.15505$1e....@newsread2.news.pas.earthlink.net...
---
carefully, you'll notice that I left out an end-of-comment token '*/' near
where I disable interrupts and translation. The stupid assmebler didn't
warn me, causing the three rather important instructions that followed to be
commented out as well. After fixing this, it works fine. I changed it to
jump 128 bytes at a time instead of 32, since that's the size of the PPC750
L2 cache block size (4 32-byte sectors) for a 1MB cache.
So, to disable all caches on the PPC750, I call l2CacheDisable passing in
the start of text (data cacheable) and 1MB. Then, I call
cacheDisable(DATA_CACHE).
Thanks
--Michael
"Michael Carr" <> wrote in message
news:100k4l6...@corp.supernews.com...
Jay
> "Jay" <jayesh.sa...@honeywell.com> wrote in message
> news:d029b3aa.04011...@posting.google.com...
> > <---> wrote in message news:<100g0l4...@corp.supernews.com>...
> > > Greetings,
> > >
> > > Can anyone tell me how cacheDisable(DATA_CACHE) behaves with respect to
> L2
> > > cache? I am suspecting (and have reason to believe, below) that it only
> > > flushes, invalidates, and disables the L1 cache.
> > >
> > vxWorks does not support L2 cache. cacheDisable() only works for L1
> cache.
> > If you have L2 cache then you are responsible for writing drivers for
> that.
>
> Okay -- next obvious question: does anyone have the algorithm for flushing
> and disabling (atomically) the PPC750 L1 and L2 caches? I've tried writing
> one that does starts with cacheDisable (flush and disable L1 flash),
> followed by simple displacement flushing (i.e., reads from text space, every
> 32 bytes), L2E clearing, and flash invalidation of L2, with interrupts
> disabled. But as soon as a re-enable interrupts, all hell breaks loose (the
> runnign task get s confused about tis stack or data on it), which implies to
> me the disaplacement flush did not clear out everything.
>
> Thoughts? My implementation is below, comments welcomed.
>
> Thanks in advance,
>
> --Michael
>
Do you have access to DINK utilities? Motorola has "recommended" cache
enable/disable methods. Can't guarantee they are always right.
Michael Carr
address (a la cacheFlush(...))
--Michael
"D." <dolis...@yahoo.com> wrote in message
news:LoyOb.15505$1e....@newsread2.news.pas.earthlink.net...
Demrala Rood
> I'm trying to flush the entire L2 cache. I.e., I am not doing a flush by
> address (a la cacheFlush(...))
You could keep thrashing around with this, but why don't you ask
Wind River for the code. It's in every 750 and 74XX BSP I've looked at.
DR