Comparison between Nehalem-EX and Power7
JF Mezei
Interesting article about upcoming chips. IA64 not mentioned. VMS mentioned.
I mention this because with the 8086 now coming to 8 cores at 64 bits,
along with power7, one wonders if Tukwila (IA64's upcoming chip) will
make any dent at all.
With the 8086 evolving at high pace, the IA64 delays will likely result
in new IA64s coming out at a time when they will already be surpassed by
the 8086. If Tukwilla's performance is not spectacularly superior to
Nehalem-EX, it would appear that the market will send a strong message
for HO-Intel to abandon IA64.
Neil Rieck
On a related note, check out the diagrams in the associated article:
Yikes! Nehalem without a Quick Path Interconnect. And the memory
controller is right on the same die as the CPU. I haven't seen
innovation like this since Alpha EV7. Alphacide was in 2002 so it only
took Intel 7 years to finally get where Alpha was. Ah, if only Carley
and Curley hadn't been seduced by the shadows (sorry, I'm re-watching
5 years of Babylon 5)
Neil Rieck
Kitchener/Waterloo/Cambridge,
Ontario, Canada.
http://www3.sympatico.ca/n.rieck/OpenVMS.html
John Wallace
> On Sep 8, 4:21 am, JF Mezei <jfmezei.spam...@vaxination.ca> wrote:
>
> >http://www.theinquirer.net/inquirer/review/1532674/power7-vs-nehalem-ex
>
> > Interesting article about upcoming chips. IA64 not mentioned. VMS mentioned.
>
> > I mention this because with the 8086 now coming to 8 cores at 64 bits,
> > along with power7, one wonders if Tukwila (IA64's upcoming chip) will
> > make any dent at all.
>
> > With the 8086 evolving at high pace, the IA64 delays will likely result
> > in new IA64s coming out at a time when they will already be surpassed by
> > the 8086. If Tukwilla's performance is not spectacularly superior to
> > Nehalem-EX, it would appear that the market will send a strong message
> > for HO-Intel to abandon IA64.
>
> On a related note, check out the diagrams in the associated article:
>
>
> Yikes! Nehalem without a Quick Path Interconnect. And the memory
> controller is right on the same die as the CPU. I haven't seen
> innovation like this since Alpha EV7. Alphacide was in 2002 so it only
> took Intel 7 years to finally get where Alpha was. Ah, if only Carley
> and Curley hadn't been seduced by the shadows (sorry, I'm re-watching
> 5 years of Babylon 5)
>
> Neil Rieck
> Kitchener/Waterloo/Cambridge,
> Ontario, Canada.http://www3.sympatico.ca/n.rieck/OpenVMS.html
That does look interesting doesn't it; it even looks applicable to
something I might need at work, where a high speed PCIe datalogging
card might be of value, especially if the PCIe interface is low
latency and low contention (for data going *to*, not from, main
memory).
Meanwhile, on a related note, what's the maximum physical memory on
these boxes these days? Is it different between Itanium boxes and
x86-64 boxes, and are the differences architectural (inherent in the
chip, maybe) or just related to the number of memory slots on a
motherboard?
Michael S
Obviously, a new 800-seies platform is not for those looking for max.
memory capacity. If you are lucky with motherboard you will be able to
run 4 DIMMs at 1333 MT/s. If you are less lucky the second pair of
DIMMs will get you down to 1066 MT/s.
If you need more take older more expensive 900 series (6 DIMMs).
If you need more yet, then your only option in Nehalemland is dual
Xeon 5500 series which on some motherboards supports up to 18x8 GB
DIMMs = 144 GB.
As to architectural limitations, all desktop Nehalem variants are
limited to 36-bit physical address space.
Xeon 5500 series - 40-bit physical address space.
Incoming Nehalem EX - not known yet, most likely 44 bits.
Itanium - 50 bits
In general, current incarnation of x86-64 instruction set architecture
(a.k.a. AMD64, a.k.a. Intel 64) is limited to 48-bit _virtual_
address space. That's probably would suffice for a couple of
decades.Going beyond that would require some, hopefully relatively
small, changes to system-layer architecture - may be a new page table
format. User-layer stuff shouldn't be affected.
glen herrmannsfeldt
(snip)
< In general, current incarnation of x86-64 instruction set architecture
< (a.k.a. AMD64, a.k.a. Intel 64) is limited to 48-bit _virtual_
< address space. That's probably would suffice for a couple of
< decades.Going beyond that would require some, hopefully relatively
< small, changes to system-layer architecture - may be a new page table
< format. User-layer stuff shouldn't be affected.
I haven't looked at x86-64 so closely yet.
It is usual to have multiple levels of tables to avoid large
tables with many entries, and to allow for paging of the tables.
S/370 and VAX use two levels of tables, segment/page for S/370,
and two levels of page tables for VAX.
The 64 bit extension to S/370, z/Architecture, uses five levels,
with some tricks to avoid the need for all five until addresses
get that big.
-- glen