Stack Architecture
Joel Lichtenwalner
A EConversation with tans...@postoffice.ptd.net (Roy J. Tellason)
prompts this question. Does anyone know what machines were the first in each
catagory to have a hardware implemented stack? Who invented the concept of
the stack?
To help pin it down,:
The DEC PDP-8 did not have a stack, the PDP-16 did (I think)
The DG Nova did not have a stack (later versions had one added, but that was
after the Eclipse was developed), the Eclipse did.
The IBM 360 series did not have a stack.
The IBM System/3, System/34 did not have a stack.
Boy, its been so long, I don't remember which of the micro's had a stack
implemented.
Joel in Ogden
Paul Frenger
Joel Lichtenwalner <JWill...@AOL.COM> wrote:
>A EConversation with tans...@postoffice.ptd.net
>(Roy J. Tellason) prompts this question. Does
>anyone know what machines were the first in each
>category to have a hardware implemented stack?
>Who invented the concept of the stack?
I have a copy of Adam Osborne's book,
"An Introduction to Microcomputers, Vol.1" (1976)
which discusses a stack with regard to bit-slice
CPU architecture, where the "stack of registers"
is used by a microprogram sequencer.
>The DEC PDP-8 did not have a stack ...
yes, but the PDP-8E did have a stack. The PDP-8
was a 12-bit processor, which used a conditional
skip logic rather than conditional branching (the
Microchip Technology PIC microcontrollers use
this technique too). To achieve a conditional
branch requires two instructions: one to test a
flag and skip or not skip the next instruction;
and the next instruction is an unconditional jump.
(Think about it ... it inverts the logic).
The PDP-8 instruction set was eventually put into
the Intersil IM6100 microcomputer chip. It too,
lacked a stack, but in Osborne and Kane's book,
"4 & 8-bit Microprocessor Handbook" (1981)
a hardware stack is implemented on pg.13-47 to 53
using a RAM chip and discrete logic.
If you like stacks, you ought to look into the
Forth programming language, which gives the user
direct access to both a parameter stack and the
return address stack. It's perfect for CP/M since
Forth uses very little machine resources. Go to
comp.lang.forth
and look around.
Paul Frenger
Associate Editor for Forth
ACM Sigplan Notes
xian the desk lisard
thus spake Joel Lichtenwalner in comp.os.cpm...
. A EConversation with tans...@postoffice.ptd.net (Roy J. Tellason)
. prompts this question. Does anyone know what machines were the first in each
. catagory to have a hardware implemented stack? Who invented the concept of
. the stack?
. To help pin it down,:
. The DEC PDP-8 did not have a stack, the PDP-16 did (I think)
^^^^^^^^^^
never produced, i believe. do you by any chance, mean the PDP-11?
anyway. the first machines with _hardware_ stacks were probably
(though i could be wrong) the burroughs b5000 in the states, and the
english electric kdf9 in britain (which was dated 1960). software
stacks i don't know about, but i suspect you could make a stack on the
manchester mark 1, since it had index registers.
--
xian the desk lisard -- cdah...@comp.brad.ac.uk
malformed [ red, pink and blue, but mainly purple ribbons ]
earthborn we both know it was a girl back in bethlehem
you know soft spoken changes nothing view so cruel
Allison Parent
Joel Lichtenwalner <JWill...@AOL.COM> wrote:
> A EConversation with tans...@postoffice.ptd.net (Roy J. Tellason)
>prompts this question. Does anyone know what machines were the first in each
>catagory to have a hardware implemented stack? Who invented the concept of
>the stack?
All of the intel designs and their followon as well as all of the
motorola designs have a hardware stack implemted in the instruction
set. The PDP-11 had a stack as did the PDP10 and the erlier versions
of the 10. MAny of the single chip four bit cpus <TI1000, NEC 5xx and
75xx > have a hardware stack.
Chips that didn't included the SC/MP, CDP1801/2/3, TI9900.
I may add the PDP-8 and the T1-9900 both had a stack of a kind as they
did automagically store the return addrtesses. The PDP-8 was creative
in saving registers by saving the called (JSR) address in the first
word prior to the subroutine. The return was a JMP I instruction. So
automatic nesting of calls and returns existed. What they didn't have
was specific PUSH or POP instructions. Many of the machines
mentioneddid however have a store via some register or indirect
address with auto increment/decrement that allowed the easy creation
of stack ordered data.
Some of the machines you listed also used similar tricks such as
store/load via indirect addresses with auto increment/decrement.
What they lack to make it obvious is an explicit stack pointer
register.
Allison
Roy J. Tellason
Joel Lichtenwalner wrote:
>
> A EConversation with tans...@postoffice.ptd.net (Roy J. Tellason)
> prompts this question. Does anyone know what machines were the first in each
> catagory to have a hardware implemented stack? Who invented the concept of
> the stack?
> after the Eclipse was developed), the Eclipse did.
> The IBM 360 series did not have a stack.
> The IBM System/3, System/34 did not have a stack.
> Boy, its been so long, I don't remember which of the micro's had a stack
> implemented.
> Joel in Ogden
I don't remember too many of the specifics, but the place where I picked up a few
tidbits about that PDP-8 was in Ted Nelson's "Computer Lib/Dream Machines". This was
originally published in a rather oddball format (like an "Ace Double", if you know
about them) back in 1974, I latched on to a copy in about '78 or so. It was later
re-issued by Microsoft Press (?!), in a somewhat smaller format with both "halfs"
facing the same way and at a substantially higher price than the original edition.
You might try and see if you can latch on to a copy of this, as it gives some
interesting historical perspective.
Nelson has some unique visions of what can be done with computers, going back to the
sixties. Some of his ideas are never going to pan out the way he envisioned them (but
then, there are some interesting twists there...) and there's lots of interesting
history in there.
I won't part with my copy! <g>
ttyl
Alan Cox
In article <4p1nlh$l...@sjx-ixn4.ix.netcom.com>,
Paul Frenger <pfre...@ix.netcom.com> wrote:
>yes, but the PDP-8E did have a stack. The PDP-8
>was a 12-bit processor, which used a conditional
>skip logic rather than conditional branching (the
>Microchip Technology PIC microcontrollers use
>this technique too). To achieve a conditional
Its a very good scheme. Similar techniques are coming back into vogue with
heavily pipelined processors. The Intel P6 adds CMOV (conditional move) to
avoid branches, and the ARM elegantly allows condition codes on ANY
instruction.
>If you like stacks, you ought to look into the
A stack in hardware is just a special case these days, and one best done
in software. No doubt that makes forth people happier since they like
two stacks.
Cox Alan ;)
--
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+44 1792 422028 (Cabletel) | Custom Linux Software Projects.
Sonix 28.8K [33.6 soon] | Linux Consultancy.
Paul Frenger
Allison Parent <alli...@world.std.com> () writes:
>All of the Intel designs ... as well as all of the
>Motorola designs have a hardware stack implemted in
>the instruction set. Chips that didn't included the
>SC/MP, CDP1801/2/3, TI9900.
Well, yes and no. What is a "stack"? Do you have to
have a PUSH and POP instruction in order to have a
true stack? My authority for the following is
Osborne's books:
"4 & 8-Bit Microprocessor Handbook"
McGraw-Hill (1981)
"16-Bit Microprocessor Handbook"
McGraw-Hill (1981)
The former resource says (pg.3-3) that the SC/MP II
has 3 pointer registers, any of which can be used as
a stack pointer (he suggests P2 as a possibility).
There was no specific PUSH / POP instruction.
The same might be said of the RCA 1802. It had 16
pointer registers. Any might be used for a stack, but
on pg.12-3 it says that the 1802 uses R2 as a stack
pointer on RESET. Again, no PUSH / POP instructions;
you had to use a cumbersome "standard call and return"
software routine involving 3 registers to accomplish
this. When the 1802 was upgraded to the 1804/5/6 series,
this "standard call and return" setup was made into a
hardwired setup: SCAL / SRET performed your PUSH / POP
duties.
The latter resource talks about the TMS9900 on pg.3-1
and following. The TI chip was interesting in that its
16 pointer registers were in RAM, not on-chip. You could
perform a "context switch" and point a "workspace
register" at a different place in RAM. In effect, you
had not only multiple potential stacks, but multiple
potential stack pointers. You still don't have a PUSH /
POP instruction, but can achieve the same effect.
The TMS 9900 was first produced in 1976, well before
the "modern era", at a time when designers were casting
about for architectural ideas. The fusion of hardware
capabilities on-chip, with corresponding CPU instructions,
left a little to be desired.
What's so great about (one or more) stacks? Because they
are zero-address devices. You don't need an address in
memory to use them; you only need to increment or decrement
a pointer to find the data stored therein (ie: PUSH or POP,
whichever is appropriate).
I like stacks; also I like linked lists, trees, arrays and
(least) heaps. I generally program in Forth, which gives me
control over the parameter and return stacks EXPLICITELY.
I guess I must be a control freak!!
Paul Frenger
Associate Editor for Forth
ACM Sigplan Notices
Mathias Niemz
Im Artikel <96060322403...@emout17.mail.aol.com>, Joel Lichtenwalner (JWill...@AOL.COM) schreibt
> A EConversation with tans...@postoffice.ptd.net (Roy J. Tellason)
>prompts this question. Does anyone know what machines were the first in each
>catagory to have a hardware implemented stack? Who invented the concept of
>the stack?
> To help pin it down,:
>The DEC PDP-8 did not have a stack, the PDP-16 did (I think)
>The DG Nova did not have a stack (later versions had one added, but that was
>
You forgot good old 6502, which has just a fixed stack....
-----------------------------------------------------------------------------
Snailmail: Mathias Niemz - Lisztstrasse 11 - 31141 Hildesheim - Germany
E-Mail: Internet: m...@huckup.winnet.de Compuserve: 76206,3341 AOL: MNiemz
Phone: (privat): +49-5121-876 932 or (business): 15921 Fax: 15405 (G2/G3)
Visit my homepage at http://ourworld.compuserve.com/homepages/Mathias_Niemz
-----------------------------------------------------------------------------
Some software seals should be labeled "ABANDON HOPE ALL YE WHO ENTER HERE".
Joel Lichtenwalner
xian the desk lisard asks, reference my reference to a PDP-16:
> Never produced, i believe. do you by any chance, mean the PDP-11?
Yes.
Guesses are now:
1st European stack machine is English Electric KDF9 (1960) (xian the desk
lisard)
1st US stack machine is Burroughs B5000 (xian the desk lisard)
Can anyone confirm or beat these guesses?
Roger Ivie
In article <DsHtL...@world.std.com>, alli...@world.std.com (Allison Parent) writes:
> I may add the PDP-8 and the T1-9900 both had a stack of a kind as they
> did automagically store the return addrtesses. The PDP-8 was creative
> in saving registers by saving the called (JSR) address in the first
> word prior to the subroutine. The return was a JMP I instruction. So
> automatic nesting of calls and returns existed.
The PDP-8 subroutine call is nothing like a stack. To see why, just try to
recurse. Or rather, recurse and then try to get back to the original caller.
I'm also not sure of how creative it was; several processors around about
that time used the same scheme.
I believe the Intersil PDP-8 on a chip had a stack, but it was
manipulated as an I/O device rather than really being part of the processor.
This was necessary since the Intersil devices booted from a ROM and the
PDP-8 subroutine calling instructions are not ROM-friendly.
--
-------------------------+---------------------------------------------
Roger Ivie | P v Q -> P
iv...@cc.usu.edu | -- Gordon B. Hinckley
http://cc.usu.edu/~ivie/ |
Holger Petersen
pfre...@ix.netcom.com(Paul Frenger) writes:
>To achieve a conditional
>branch requires two instructions: one to test a
>flag and skip or not skip the next instruction;
>and the next instruction is an unconditional jump.
>(Think about it ... it inverts the logic).
Which takes us back to CP/M: In it's BDOS (and CCP), which
was written in PL/M, you'll find a lot of places like:
; make for ZERO Flag
jp z, Label
ret
Label: ; go further
instead of the existing "RET NZ".
[perhaps Z/NZ reversed]
I still miss 'RET on Condition' in 8086-ASM...
Greetings, Holger
Joel Lichtenwalner
pfre...@IX.NETCOM.COM (Paul Frenger)
> Yes, but the PDP-8E did have a stack
You have now confused me. I never worked with the PDP-8E, but my wife
did. I worked with the IM-6100, you mentioned, and it didn't have a stack,
but it did claim to be a duplicate of the PDP-8E. My wife states
catagorically that the PDP-8 didn't have a stack.
If a stack was placed on the PDP-8, there was no holes in the
instruction set to be able to access it unless it was considered an I/O
device.
In addition, Edison DeCastro designed the DG Nova as an upgrade of the
PDP-8 instruction set. It didn't have a stack until late in its lifecycle
when the Micro-nova was given a stack. The Nova did have some holes in its
instruction set as there were several ways to do things like clear the
accumulator and they pre-empted all but one of these and made them new
instructions. They may have used these new instructions for the stack, but I
never programmed a Nova with a stack, so I don't know.
On top of that, the 8 architecture was made such that a stack would have
been of limited value. A call to a subroutine actually stuffed the return
address in memory at the address of the call and began execution at the next
location. To use a stack, the subroutine would have to pick up the return
address from memory and stuff it on the stack, unless, of course, there was
an alternate subroutine call instruction introduced with the stack.
I don't consider myself an expert on the PDP-8, so if you can explain, I
would appreciate it.
Joel
Joel Lichtenwalner
That's a good question. I guess I should have defined a stack before I
asked the question. To me, a hardware stack has to have hardware
instructions (as opposed to macro's) that implement it, including a method
whereby a subroutine call puts the return address on the stack.
That is, a computer, to have a hardware stack, must have subroutine call
and interrupt handling instructions that put the address onto the stack and
return instructions that take it off. The Motorola 146805 series has just
that, but no push or pop and no access to the stack pointer register except
the reset which points it at a specific location. Very frustrating, but
still a stack.
Joel
Paul Schlyter
In article <4...@huckup.winnet.de>, Mathias Niemz <m...@huckup.winnet.de> wrote:
> Im Artikel <96060322403...@emout17.mail.aol.com>, Joel Lichtenwalner (JWill...@AOL.COM) schreibt
>> A EConversation with tans...@postoffice.ptd.net (Roy J. Tellason)
>>prompts this question. Does anyone know what machines were the first in each
>>catagory to have a hardware implemented stack? Who invented the concept of
>>the stack?
>> To help pin it down,:
>>The DEC PDP-8 did not have a stack, the PDP-16 did (I think)
>>The DG Nova did not have a stack (later versions had one added, but that was
>>after the Eclipse was developed), the Eclipse did... (stuff deleted)
>
> You forgot good old 6502, which has just a fixed stack....
i.e. it didn't use main RAM for the stack!
However, among early mainframes the CPU often lacked any stack
support. This is one of the reasons that ancient languages like
FORTRAN does not allow recursive function calls: the return address
were often stored within the code of the called function! Thus (if
we use 80x86 assembly as an example) instead of doing:
call sub
......
sub: (some code)
ret
one would do:
mov [sub], offset next
jmp sub+2
next:
.......
sub: dw 0 ; Return address stored here
(some code)
jmp [sub]
This will allow you to call subroutines without using the stack, but
you canNOT do recursive subroutine calls like this!
--
----------------------------------------------------------------
Paul Schlyter, Swedish Amateur Astronomer's Society (SAAF)
Grev Turegatan 40, S-114 38 Stockholm, SWEDEN
e-mail: pau...@saaf.se p...@home.ausys.se
Paul Frenger
Roger Ivie <iv...@cc.usu.edu> wrote:
>I believe the Intersil PDP-8 on a chip had a stack, but
>it was manipulated as an I/O device rather than really
>being part of the processor. This was necessary since the
>Intersil devices booted from a ROM and the PDP-8 subroutine
>calling instructions are not ROM-friendly.
Please see my message #15075, re: the Intersil IM6100. The
stack was created with external RAM and discrete logic, per
Adam Osborne's book (mentioned in the message).
The PDP-8 stored a subroutine return address inline with
the calling program code. Hence it was not suited either to
recursion or to execution from ROM (can't write the return
address to ROM, silly!).
If the program was copied to RAM, it had a better chance of
working!
Paul Frenger
In <96060517465...@emout17.mail.aol.com> Joel Lichtenwalner
<JWill...@AOL.COM> writes:
>
>pfre...@IX.NETCOM.COM (Paul Frenger)
>> Yes, but the PDP-8E did have a stack
>
>You have now confused me. I never worked with the PDP-8E, but
>my wife did. I worked with the IM-6100, you mentioned, and it
>didn't have a stack, but it did claim to be a duplicate of the
>in the instruction set to be able to access it unless it was
>considered an I/O device.
>... n top of that, the 8 architecture was made such that a stack
>would have been of limited value. A call to a subroutine actually
>stuffed the return address in memory at the address of the call
>and began execution at the next location. To use a stack, the
>subroutine would have to pick up the return address from memory
>and stuff it on the stack, unless, of course, there was an
>alternate subroutine call instruction introduced with the stack.
Everything you say above is true. See message #15075 for the
reference to the Intersil IM6100 in Adam Osborne's book, for
how to create a stack as an I/O device.
Some confusion may come into play since DEC sold a dedicated word
processing machine sometime in the late 1970's or early 1980's. A
contemporary trade journal nentioned how this device was based on a
version of the PDP-8E, and that it had been upgraded to a hardware
stack configuration (sorry, reference lost in antiquity). Now DEC
produced "cheap" or micro versions of its PDP-11 minicomputer with
a "LSI-11" moniker. Heathkit sold a version of this for years.
I can't be sure, but I think DEC's word processor PDP-8E was an
in-house minicomputer "knock-off" implemented in a similar fashion.
It may even have been built with the Intersil part (I really don't
know). Intersil made an IM6101 PIE ("parallel interface element")
to serve as a kind of port; and the IM6102 MEDIC (memory expander
and bus controller). These additional chips are described in the
Osborne book in detail.
Harris Semi was a second source to Intersil for the IM6100 et al.
I hope I haven't further muddled things up; this is ancient stuff,
to be sure. But it points out that stacks can be added-on to micros
if there is a memory access technique available and you are clever
with discrete logic chips.
Alan Cox
In article <4p5rfg$8...@electra.saaf.se>,
Paul Schlyter <pau...@electra.saaf.se> wrote:
>
>sub: dw 0 ; Return address stored here
> (some code)
> jmp [sub]
>
>This will allow you to call subroutines without using the stack, but
>you canNOT do recursive subroutine calls like this!
It was often possible to stick code equivalent to this into the program
however. And nothing (even a self modifying constant load for doing the
stack pointer was to foul).
After that we had the other extreme like the Honeywell's with an opcode for
"call function with variable number of arguments".
sub dw 0 ; Return here
call stuff_func
blah blah
call unstuff_func
jmp accumulator
and stuff func tended to do sick and foul things like
stuff_func dw 0
mov [stuff_func], acc # Our caller
mov [acc], acc # Our callers caller
L1: mov acc, [stackptr] # Save it
selfmodify L1
selfmodify L2 # see below
jmp [stuff_func]
unstuff_func dw 0
L2: mov [stackptr], acc
selfmodify L1
selfmodify L2
mov [unstuff_func], acc2 # Caller
mov [acc2], acc # Change callers caller
jmp [unstuff_func]
--
(3) With sufficient thrust, pigs fly just fine. However, this is
not necessarily a good idea. It is hard to be sure where they
are going to land, and it could be dangerous sitting under them
as they fly overhead. -- RFC 1925 - Fundamental truths of networking
xian the desk lisard
thus spake Alan Cox in comp.os.cpm...
. A stack in hardware is just a special case these days, and one best done
. in software. No doubt that makes forth people happier since they like
. two stacks.
three if you indulge in the anathema of floating point math. |:>
prolog needs up to 8 stacks, according to a snippet i saw in byte
once.
--
xian the desk lisard -- cdah...@comp.brad.ac.uk -- self-abusive recluse
john r pierce
iv...@cc.usu.edu (Roger Ivie) wrote:
>In article <DsHtL...@world.std.com>, alli...@world.std.com (Allison Parent) writes:
>> I may add the PDP-8 and the T1-9900 both had a stack of a kind as they
>> did automagically store the return addrtesses. The PDP-8 was creative
>> in saving registers by saving the called (JSR) address in the first
>> word prior to the subroutine. The return was a JMP I instruction. So
>> automatic nesting of calls and returns existed.
>
>The PDP-8 subroutine call is nothing like a stack. To see why, just try to
>recurse. Or rather, recurse and then try to get back to the original caller.
>I'm also not sure of how creative it was; several processors around about
>that time used the same scheme.
I can vouch that the IBM 1130 (may it rest in pieces) did the exact
same thing... 'call' was a 'branch and store index' instruction
(BSI?), 'ret' was a 'branch indirect' (BR I?)... The return address
was stored at the first word of the subroutine. I believe the IBM
1130 predated the pdp8 by more than a few years, it was obsolete in
1972 when I programmed them.
ric...@warwick.net
Paul Schlyter (pau...@electra.saaf.se) wrote:
: In article <4...@huckup.winnet.de>, Mathias Niemz <m...@huckup.winnet.de> wrote:
:
: > Im Artikel <96060322403...@emout17.mail.aol.com>, Joel Lichtenwalner (JWill...@AOL.COM) schreibt
: >> A EConversation with tans...@postoffice.ptd.net (Roy J. Tellason)
: >>prompts this question. Does anyone know what machines were the first in each
: >>catagory to have a hardware implemented stack? Who invented the concept of
: >>the stack?
: >> To help pin it down,:
: >>The DEC PDP-8 did not have a stack, the PDP-16 did (I think)
: >>The DG Nova did not have a stack (later versions had one added, but that was
: >>after the Eclipse was developed), the Eclipse did... (stuff deleted)
: >
: > You forgot good old 6502, which has just a fixed stack....
:
: And the gool ol' 8008 had a hardware stack of 6 levels inside the CPU,
: i.e. it didn't use main RAM for the stack!
I looked up the 4004 today, it has an address stack of 4 12-bit registers,
counting the instruction pointer.
Allison Parent
Joel Lichtenwalner <JWill...@AOL.COM> wrote:
> You have now confused me. I never worked with the PDP-8E, but my wife
>did. I worked with the IM-6100, you mentioned, and it didn't have a stack,
>but it did claim to be a duplicate of the PDP-8E. My wife states
>catagorically that the PDP-8 didn't have a stack.
None of the non-chip versions of the PDP-8 L/M/E/I/S had a stack.
The 8A however did as did the 6120 version on a chip. It's not to say
an earlier 8 could not have a stack, as it could and was implemented
using IOT hardware and instructions along with the fact that the
non-chip 8s registers were totally accessable on the bus by
manipulating various control lines. The PDP-8 was a crude machine
that was easy to interface and extend as needed, this was why it was
successful compared to earlier machines.
I know as I had an 8E, an 8A . I still have the 6100 and 6120
versions. The chip version are far slower than the originals.
But, they are smaller and warm the room less.
Allison
Allison Parent
pfre...@ix.netcom.com(Paul Frenger) wrote:
>Everything you say above is true. See message #15075 for the
>reference to the Intersil IM6100 in Adam Osborne's book, for
>how to create a stack as an I/O device.
DED didn't do it that way.
>Some confusion may come into play since DEC sold a dedicated word
>processing machine sometime in the late 1970's or early 1980's. A
WPS-8, based initally on the PDP-8E and later upgraded to an 8A
which had access to 64k of memeory, hardware stacks and faster.
It was capable of handling 16 workstations (vt52s) and several
printers which could be both line printers or daisy wheel LQP.
In later years the multiuser WPS machine gave way to the individual
LSI powered DECMATE I <6100> then the later Decmate II and III <6120>.
I still have and use a DecmateIII as it is a nice word processor and
makes a fair vt52/100/200 terminal.
>version of the PDP-8E, and that it had been upgraded to a hardware
>stack configuration (sorry, reference lost in antiquity). Now DEC
That was the 6120 version of the 6100.
>produced "cheap" or micro versions of its PDP-11 minicomputer with
>a "LSI-11" moniker. Heathkit sold a version of this for years.
That was the PDP-11 using the WD-13 chipset. Very popular machine.
Allison
Allison Parent
iv...@cc.usu.edu (Roger Ivie) wrote:
>The PDP-8 subroutine call is nothing like a stack. To see why, just try to
>recurse. Or rather, recurse and then try to get back to the original caller.
>I'm also not sure of how creative it was; several processors around about
>that time used the same scheme.
I didn't say it was perfect. ;-) recursion required using the
Auto increment register to fake a stack. It did however do the job
with very little hardware. We have to remember that it took lots of
transisters back then to implement a register and even the early IC
machines like the PDP-8 still required several Chips to create a
register.
>I believe the Intersil PDP-8 on a chip had a stack, but it was
The base 6100 was PDP-8E/I abd had no stack. The 6120 did have
the port implemented stack, actually there were two.
>PDP-8 subroutine calling instructions are not ROM-friendly.
No they weren't but back then with CORE who needed rom. ;-)
Allison
Dave
Joel Lichtenwalner <JWill...@AOL.COM> wrote:
>Yes.
Confirmed as to the KDF-9. I can't speak for the Burroughs machine.
-- Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger da...@opera.iinet.net.au
servers da...@iinet.net.au
fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34
Paul Frenger
Allison Parent <alli...@world.std.com> wrote:
>pfre...@ix.netcom.com (Paul Frenger) wrote:
>
>>Everything you say above is true. See message #15075 for the
>>reference to the Intersil IM6100 in Adam Osborne's book, for
>>how to create a stack as an I/O device.
>
>>Some confusion may come into play since DEC sold a dedicated word
>>processing machine sometime in the late 1970's or early 1980's. A
>
>WPS-8, based initally on the PDP-8E and later upgraded to an 8A
>which had access to 64k of memeory, hardware stacks and faster.
>It was capable of handling 16 workstations (vt52s) and several
>printers which could be both line printers or daisy wheel LQP.
>
>In later years the multiuser WPS machine gave way to the individual
>LSI powered DECMATE I <6100> then the later Decmate II and III <6120>.
>
>I still have and use a DecmateIII as it is a nice word processor and
>makes a fair vt52/100/200 terminal.
>
>>version of the PDP-8E, and that it had been upgraded to a hardware
>>stack configuration (sorry, reference lost in antiquity). Now DEC
>
>That was the 6120 version of the 6100.
>
>>produced "cheap" or micro versions of its PDP-11 minicomputer with
>>a "LSI-11" moniker. Heathkit sold a version of this for years.
>
>That was the PDP-11 using the WD-13 chipset. Very popular machine.
>
>Allison
Thanks very much for the clarifications. To focus on the last point,
Western Digital made a chipset which was a "Pascal Engine". It used
p-code (an intermediate representation of Pascal source) which it
interpreted. I was never sure, but the Pascal p-code interpreter
looked a lot like the LSI-11 chipset WD made (four big chips). Even
RCA got into the act. It created a version of the 1802/1804 which
interpreted "micro Concurrent Pascal", a multitasking Pascal.
My interest in stacks relates to Forth. The PDP-11 was considered
an excellent Forth machine. I can't recall anyone porting Forth to
the PDP-8? I put a modified FIG-Forth on the RCA 1802 and, even
without traditional PUSH / POP instructions, it ran Forth just fine.
I'm amazed by all this nostalgia for the PDP-8. But it just goes to
show: no computer is obsolete until the last remaining user shuts
it down forever (CP/M users, take heart!).
bill_h
I agree.....Burroughs was first.....I'm thinking 1959 or so (stacks)
Roger Ivie
In article <31b8696d...@news.scruznet.com>, pie...@scruznet.com (john r pierce) writes:
> I can vouch that the IBM 1130 (may it rest in pieces) did the exact
> same thing... 'call' was a 'branch and store index' instruction
> (BSI?), 'ret' was a 'branch indirect' (BR I?)... The return address
> was stored at the first word of the subroutine. I believe the IBM
> 1130 predated the pdp8 by more than a few years, it was obsolete in
> 1972 when I programmed them.
Bear in mind that the PDP-8 line started in 1963 with the PDP-5...
I was under the impression that the 1130 was built with /360 parts, which would
put it around the same time frame. For the life of me, I can't recall how the
PDP-1 and PDP-4 did subroutines (not that I've ever used a PDP-1 or a PDP-4,
mind you).
Roger Ivie
In article <DsnH6...@world.std.com>, alli...@world.std.com (Allison Parent) writes:
> WPS-8, based initally on the PDP-8E and later upgraded to an 8A
> which had access to 64k of memeory, hardware stacks and faster.
Hmm, according to one source I've seen (and which escapes me at the moment;
perhaps it was Bell&Newell?), the PDP-8 never got faster in all the 30 years
it was being sold. Except for the PDP-5 and the PDP-8/s (which were much
slower), all of the PDP-8 processors were roughly the same speed.
>>produced "cheap" or micro versions of its PDP-11 minicomputer with
>>a "LSI-11" moniker. Heathkit sold a version of this for years.
>
> That was the PDP-11 using the WD-13 chipset. Very popular machine.
I was under the impression that Heathkit resold the DEC processor, which
was being marketed to OEMs at the time. The Western Digital version of the
chipset had some opcodes shuffled around, according to rumor.
Roger Ivie
In article <DsnGD...@world.std.com>, alli...@world.std.com (Allison Parent) writes:
> iv...@cc.usu.edu (Roger Ivie) wrote:
>
>>The PDP-8 subroutine call is nothing like a stack. To see why, just try to
>>recurse. Or rather, recurse and then try to get back to the original caller.
>>I'm also not sure of how creative it was; several processors around about
>>that time used the same scheme.
>
> I didn't say it was perfect. ;-) recursion required using the
> Auto increment register to fake a stack.
No, but someone did claim it was a stack. It isn't.
> It did however do the job
> with very little hardware. We have to remember that it took lots of
> transisters back then to implement a register and even the early IC
> machines like the PDP-8 still required several Chips to create a
> register.
Ah, so you've never seen a "classic" PDP-8 (you know, the PDP-8/nothing,
built from paddle cards stuffed with transistors and yet still small enough
to be sold as a tabletop machine)?
xian the desk lisard
thus spake Paul Frenger in comp.os.cpm...
. interpreted. I was never sure, but the Pascal p-code interpreter
. looked a lot like the LSI-11 chipset WD made (four big chips). Even
that's because it was the same core chipset; only the microcode was
different.
. RCA got into the act. It created a version of the 1802/1804 which
. interpreted "micro Concurrent Pascal", a multitasking Pascal.
and didn't the 1805 have extra instructions to enhance forth
performance?
. My interest in stacks relates to Forth. The PDP-11 was considered
. an excellent Forth machine. I can't recall anyone porting Forth to
. the PDP-8?
byte forth issue, charles moore's description of forth's evolution,
aug 1980 pp100- (i think). he enumerates the machines on which he can
remember putting forth, and the pdp8 is in there. (be fun, though.
12 bit cells... |:> )
. I put a modified FIG-Forth on the RCA 1802 and, even
. without traditional PUSH / POP instructions, it ran Forth just fine.
but what was the speed like?
xian the desk lisard
thus spake bill_h in comp.os.cpm...
. I agree.....Burroughs was first.....I'm thinking 1959 or so (stacks)
the burroughs and kdf9 machines were launched pretty much concurrently
(source: early british computers, simon lavington, manchester
university press). different emphases, since burroughs built an
"algol machine" and english electric just wanted to make it fast, and
different sides of the atlantic, but same core concept.
Bill Haygood
: thus spake Paul Frenger in comp.os.cpm...
: My interest in stacks relates to Forth. The PDP-11 was considered
: an excellent Forth machine. I can't recall anyone porting Forth to
: the PDP-8?
I actually did some exploratory work to implement Forth on the PDP-8,
although after puzzling over mechanisms to implement multi-field
memory for Forth basic instructions, I just basically decided that
it would not be an efficient implementation. After reviewing the
PDP-11 instruction set, however, I thought that machine would make a
great Forth machine.
Bill
Allison Parent
iv...@cc.usu.edu (Roger Ivie) wrote:
>perhaps it was Bell&Newell?), the PDP-8 never got faster in all the 30 years
>it was being sold. Except for the PDP-5 and the PDP-8/s (which were much
>slower), all of the PDP-8 processors were roughly the same speed.
Not entirely true. The 8E/L/M/I/F were the same basic CPU. The 8S
was serial arithmatic so it was very slow. The 6100/6120 are
microcoded CMOS and most versions are quite slow compared to the
original. The 8A was the fastest though by only a little bit and it
was generally seen running WPS only.
Allison
>>>produced "cheap" or micro versions of its PDP-11 minicomputer with
>>>a "LSI-11" moniker. Heathkit sold a version of this for years.
>>
>> That was the PDP-11 using the WD-13 chipset. Very popular machine.
>I was under the impression that Heathkit resold the DEC processor, which
>was being marketed to OEMs at the time. The Western Digital version of the
>chipset had some opcodes shuffled around, according to rumor.
Allison Parent
iv...@cc.usu.edu (Roger Ivie) wrote:
>Ah, so you've never seen a "classic" PDP-8 (you know, the PDP-8/nothing,
>built from paddle cards stuffed with transistors and yet still small enough
>to be sold as a tabletop machine)?
Wrong, I have three modules from one but there were still some ICs in
it. I also played with a primo PDP-5 once. Almost had a PDP-6 and 7
both museum quality and working!
Allison
Roger Ivie
The "ICs" in the "classic" PDP-8 are strictly passives AFAIK; i.e.,
resistor networks.
--
-------------------------+---------------------------------------------
Roger Ivie | "Irony can be pretty ironic sometimes."
iv...@cc.usu.edu | -- Frank Drebin
http://cc.usu.edu/~ivie/ |
Roger Ivie
In article <DsyID...@world.std.com>, alli...@world.std.com (Allison Parent) writes:
> iv...@cc.usu.edu (Roger Ivie) wrote:
>
>>Ah, so you've never seen a "classic" PDP-8 (you know, the PDP-8/nothing,
>>built from paddle cards stuffed with transistors and yet still small enough
>>to be sold as a tabletop machine)?
>
> Wrong, I have three modules from one but there were still some ICs in
> it. I also played with a primo PDP-5 once. Almost had a PDP-6 and 7
Say, did you do enough playing with the PDP-5 to answer some questions for
me? Do you know the restrictions on combined microinstructions? I've also
heard there's some difference between the PDP-5's and the PDP-8's handling
of IOT instructions (the fellow who told me this couldn't remember what the
difference was; he was brought into DEC to work on the PDP-8/i and the
PDP-5 was done by a different group). Do you know what that difference might
be?
I have a programming card for a PDP-5 which has a section titled "combined
operate microinstructions"; what I don't know is if this section lists all
the legal PDP-5 combined instructions or only the ones the author of the
card thought might be interesting.
The comment about the IOT difference is a complete mystery to me. Offhand,
I suspect it may be the case that PDP-5 can take only one skip on an IOT
while a PDP-8/i or /l can do up to three (a PDP-8/e, of course, can do
just about anything you want it to do). I've not actually _used_ a "classic"
8, so I don't know how its IOTs were implemented. I've also never used a -5,
but I do have a few bits (front panel and a couple of miscellaneous modules).
Allison Parent
iv...@cc.usu.edu (Roger Ivie) wrote:
>The "ICs" in the "classic" PDP-8 are strictly passives AFAIK; i.e.,
>resistor networks.
Roger,
No some were a version of RTL called utilogic, very simple gates and
the most complex part being JK ff <about 20 transisters>. Some of the
others were analog and used for sense amps in the core. The first 8
was very laden with real transisters though.
Allison
Allison Parent
iv...@cc.usu.edu (Roger Ivie) wrote:
>Say, did you do enough playing with the PDP-5 to answer some questions for
>me? Do you know the restrictions on combined microinstructions? I've also
Too long ago to remeber.
>heard there's some difference between the PDP-5's and the PDP-8's handling
>of IOT instructions (the fellow who told me this couldn't remember what the
>difference was; he was brought into DEC to work on the PDP-8/i and the
>PDP-5 was done by a different group). Do you know what that difference might
>be?
>I have a programming card for a PDP-5 which has a section titled "combined
>operate microinstructions"; what I don't know is if this section lists all
>the legal PDP-5 combined instructions or only the ones the author of the
>card thought might be interesting.
Same as the 8 in that they described the likely and most useful and
later the ones supported and gaurenteed to work on any 8.
>The comment about the IOT difference is a complete mystery to me. Offhand,
>I suspect it may be the case that PDP-5 can take only one skip on an IOT
Uncertain on this, not enough memory of the 5.
>while a PDP-8/i or /l can do up to three (a PDP-8/e, of course, can do
>just about anything you want it to do). I've not actually _used_ a "classic"
>8, so I don't know how its IOTs were implemented. I've also never used a -5,
>but I do have a few bits (front panel and a couple of miscellaneous modules).
Sound like youve confused a data break (bus grant for DMA like ops)
from IOT ops. The 8 IOT could do many different operations, simple
output from the acc or input are the most obvious and similar to the
5. The difference was if you wanted to do something like capture the
PC and force a new value, the 5 didn't if memory serves. The 8 IOT
as a reference to micro users is very different from an INP or out.
Other than the silicon versions of the PDP-8 there are no micros that
have IO that is remotely similar <the DG Nova may>. The IOT opcode
only told the cpu that an IO operation of some type was to happen and
and to monitor the C0, C1, C2 and skip lines on the bus for what to
do. The device addressed in the lower 9 bits determined the
operation. By convention the lowest order 3 bits encoded the
operation and the six next higher the device. Common IOTs would skip
if device flag was set or not set. Other would send a word or get a
word to the accumulator. The possibilities could be to complex like
get the word if ready otherwise skip, that would be like an 8080:
in status
ani ready
jnz skip
in data
SKIP:
This made the IOT very powerful and compact. It's control line also
allowed operations like capture PC, add a value to it and replace the
PC. This allowed the pdp-8a stacks to be implemented as well as
memory extension beyond the basic 4k words.
The 5 had more limited capabilites and I believe it was in the area of
doing multiple operations in the same iot.
Allisond
Roger Ivie
In article <Dt26q...@world.std.com>, alli...@world.std.com (Allison Parent) writes:
> Sound like youve confused a data break (bus grant for DMA like ops)
I don't think so, although I've not (yet) designed hardware for any 8s.
> have IO that is remotely similar <the DG Nova may>. The IOT opcode
> only told the cpu that an IO operation of some type was to happen and
> and to monitor the C0, C1, C2 and skip lines on the bus for what to
> do. The device addressed in the lower 9 bits determined the
On the 8/E and other OMNIBUS CPUs, skip was done byy an "add this value
to the PC" operation, so you could skip anywhere you wanted within the current
instruction field, IIRC.
Earlier 8s had a different scheme for I/O. Where the 8/E pretty much
and turned timing over to the peripheral, the 8/i and the like would generate
up to three timing pulses (depending on which of the low-order three bits
were set in the IOT instruction). At each pulse you had an opportunity to
examine the accumulator, clear the accumulator, OR a value into
the accumulator, and/or skip. That's why I think machines earlier than
OMNIBUS could skip up to three times in one IOT.
Of course, I may be totally out to lunch here; like I said, I've not
designed hardware for any 8s and I don't have an 8 old enough to predate
OMNIBUS.
David Director
As long as we're discussing old DEC machines, does anybody out there
remember the LINC (Laboratory Instrument Computer) that they built
back in the middle '60s? 2K of 12-bit memory, a couple of DECtapes,
built-in A/D and D/A convertors, and a 5" Tektronics bit-mapped display
for output.
They later married it to a PDP-8 to make the PDP-12, possibly the
world's first dual-processor system...
-- David
A.R. Duell
David Director <da...@grtadv.shl.com> writes:
[Linc]
>They later married it to a PDP-8 to make the PDP-12, possibly the
>world's first dual-processor system...
Well, according to the PDP12 printset (schematics), there's only one
processor in there, but it can execute either PDP8 or LINC ('PDP12')
instructions. It was not strictly a dual-processor machine, as it
couldn't execute 2 instructions at once.
>-- David
--
-tony
ar...@eng.cam.ac.uk
The gates in my computer are AND,OR and NOT, not Bill
Roger Ivie
In article <31C57E...@grtadv.shl.com>, David Director <da...@grtadv.shl.com> writes:
> As long as we're discussing old DEC machines, does anybody out there
> remember the LINC (Laboratory Instrument Computer) that they built
> back in the middle '60s? 2K of 12-bit memory, a couple of DECtapes,
> built-in A/D and D/A convertors, and a 5" Tektronics bit-mapped display
> for output.
Actually, it probably used LINCtapes which rumor has it were
essentially DECtapes wound the other way.
> They later married it to a PDP-8 to make the PDP-12, possibly the
> world's first dual-processor system...
Aside from all the Illiacs, I've seen stuff about a
multiprocessor machine from a company called "Ramo <something or other>".
Each processor had its own large box, including a console with
a giant screen. I found this reference in a large collection of
blurbs about machines from about 1960; it also had a blurb on the PDP-1 & PDP-3
which was rather odd in that it pushed the PDP-3 and referred to the
PDP-1 only as "the 18-bit version of the PDP-3."
xian the desk lisard
thus spake Allison Parent in comp.os.cpm...
. iv...@cc.usu.edu (Roger Ivie) wrote:
. >perhaps it was Bell&Newell?), the PDP-8 never got faster in all the 30 years
. >it was being sold. Except for the PDP-5 and the PDP-8/s (which were much
. >slower), all of the PDP-8 processors were roughly the same speed.
. Not entirely true. The 8E/L/M/I/F were the same basic CPU. The 8S
. was serial arithmatic so it was very slow. The 6100/6120 are
. microcoded CMOS and most versions are quite slow compared to the
. original. The 8A was the fastest though by only a little bit and it
. was generally seen running WPS only.
*shakes head slowly*
why would anybody feel the need to _microcode_ an implementation of
the pdp8...?
Roger Ivie
In article <4q69qg$p...@columbia.acc.brad.ac.uk>, cdah...@comp.brad.ac.uk (xian the desk lisard) writes:
> why would anybody feel the need to _microcode_ an implementation of
> the pdp8...?
Could be worse. ROMs are getting so large nowadays that it should be
possible to build a PDP-8 CPU using only ROMs and shift registers; i.e.,
_all_ computes would be done in the ROMs. My preliminary fiddling about
indicates that 512Kwords of control store should be sufficient.
john r pierce
cdah...@comp.brad.ac.uk (xian the desk lisard) wrote:
>. Not entirely true. The 8E/L/M/I/F were the same basic CPU. The 8S
>. was serial arithmatic so it was very slow. The 6100/6120 are
>. microcoded CMOS and most versions are quite slow compared to the
>. original. The 8A was the fastest though by only a little bit and it
>. was generally seen running WPS only.
>
>*shakes head slowly*
>
>the pdp8...?
I believe several ultra-low power CMOS control processors are
microcoded to sequence '1 bit' alu's (i.e. bit serial).. The mot 6803
(6804?) comes to mind. these CPUs are quite slow, and power
consumption is the overwhelming design criteria. Since even a simple
8 bit ADD instruction takes 8 or more cycles, microcode makes some
sense.
-jrp
Joel Lichtenwalner
cdah...@COMP.BRAD.AC.UK (xian the desk lisard) wrote:
> *shakes head slowly*
> why would anybody feel the need to _microcode_ an
> implementation of the pdp8...?
This does look kind of stupid from our present viewpoint, but when you
consder that the 8 was made with discrete logic and integrated circuits at a
time when 4 flip-flops in one package was considered dense packaging, it
begins to make a little more sense. Logic integrated circuits cost as much
as $150 each (I am thinking specifically of Imelco 12v logic in a half-dollar
size can, 1969) down to as little as $5 for RTL if bought in quantity.
Anything that would eliminate circuitry would cut the purchase price
considerably.
In an aplication where slow speed could be tolerated, it had its
advantages. Less circuitry meant less cost for that circuitry, less power
consumption, allowing less cost for power supplies, and therefore less heat
allowing for smaller packaging and cheaper fans and filters. When the
processor costs $20,000 and memory is $2 per (12 bit) word, anything that
would cut costs would would improve profits.
In one project I consulted on in 1972 (several years after the 8 was
considered passe'), the project was bid around a Nova 1200. It turned out
that the 1200 was too slow for the job and that the price of the upgrade to a
Nova 800, at the contractor's expense, would eat up all the profits and then
some. Fortunately, by redefinition of the data types, enough efficiency was
achieved so that the 1200 did the job.
At that time, the cost of the hardware was a major cost of the project.
Now, the cost of hardware is minimal in comparison to the cost of software.
* slow shake of the head *
My how times, they have changed.
Joel in Ogden
Dave
iv...@cc.usu.edu (Roger Ivie) wrote:
[snip]
>> They later married it to a PDP-8 to make the PDP-12, possibly the
>> world's first dual-processor system...
>Aside from all the Illiacs, I've seen stuff about a
>multiprocessor machine from a company called "Ramo <something or other>".
>Each processor had its own large box, including a console with
>a giant screen. I found this reference in a large collection of
>blurbs about machines from about 1960; it also had a blurb on the PDP-1 & PDP-3
>which was rather odd in that it pushed the PDP-3 and referred to the
>PDP-1 only as "the 18-bit version of the PDP-3."
Another old multi-processor system (ca 1963) was VERDAN - "Versatile
Digital Analyser". It had 3 engines: a basic 26-bit CPU, a "digital
differential analyser", ie a coprocessor specially tailored for
solving differential equations, and an analogue computing section. It
was used in SINS - Ships Inertial Navigation System, and also in the
British TSR-2 aircraft project.
The main CPU used a disk carrying 2k x 26-bit words (yes, a disk!),
with a bit-serial CPU. Everything built from discrete transistors,
with parts soldered on both sides of the PCB, their footprints
overlapping each other, so each masked the other's pads. A joy to work
on!
(Should I have crossposted this to comp.arch.embedded &
rec.boatanchors? :-)
xian the desk lisard
thus spake john r pierce in comp.os.cpm...
. >why would anybody feel the need to _microcode_ an implementation of
. >the pdp8...?
. I believe several ultra-low power CMOS control processors are
. microcoded to sequence '1 bit' alu's (i.e. bit serial).. The mot 6803
. (6804?) comes to mind.
6804. (also the SC/MP was bit-serial.) but can't a bit-serial
processor be controlled through logic - or is a microcoded scheme just
cheaper?
. these CPUs are quite slow, and power
. consumption is the overwhelming design criteria. Since even a simple
. 8 bit ADD instruction takes 8 or more cycles, microcode makes some
. sense.
yes, but all the same, i doubt that the 6100 was bit-serial.
(incidentally, what about the 1802? i always wondered if the 16-cycle
execution time of most instructions was significant...)
john r pierce
cdah...@comp.brad.ac.uk (xian the desk lisard) wrote:
>thus spake john r pierce in comp.os.cpm...
>
>. >why would anybody feel the need to _microcode_ an implementation of
>. >the pdp8...?
>
>. I believe several ultra-low power CMOS control processors are
>. microcoded to sequence '1 bit' alu's (i.e. bit serial).. The mot 6803
>. (6804?) comes to mind.
>
>6804. (also the SC/MP was bit-serial.) but can't a bit-serial
>processor be controlled through logic - or is a microcoded scheme just
>cheaper?
Oooh. the scramp. My mind reels to even recollect that disaster
existed! :)
Yeah, you can do it either way, but since a serial CPU requires so
many cycles to do nothing, I suspect uCode is the easy way out...
>yes, but all the same, i doubt that the 6100 was bit-serial.
>(incidentally, what about the 1802? i always wondered if the 16-cycle
> execution time of most instructions was significant...)
Oooh. COSMAC. What I said above about the SC/MP goes triple for that
one! :) Um, somehow, I suspect the 1802 was hardwired sequencers
internally...
-jrp
David Director
>
> Actually, it probably used LINCtapes which rumor has it were
> essentially DECtapes wound the other way.
>
> multiprocessor machine from a company called "Ramo <something or other>".
You're right; they were LINCtapes. I don't know about being wound
backwards, though I do have a vague recollection of the reel being
mounted on the right-hand spool, with the takeup on the left, so that
may very well have been the case. Talk about the world's simplest
tape drive: two spools and a multi-track (7 ??) head; one track had
timing marks, so it didn't matter whether the tape was at a constant
speed or not; blocks of (I think) 1K 12-bit words with an address
header, so they could be read or written in either direction. I still
have a couple buried in a box somewhere, with a few programs on them.
As to your other comment, it was probably Bunker-Ramo, a large
defense contractor of that time.
-- David
Roger Ivie
In article <31D296...@grtadv.shl.com>, David Director <da...@grtadv.shl.com> writes:
>
> You're right; they were LINCtapes. I don't know about being wound
> backwards, though I do have a vague recollection of the reel being
> mounted on the right-hand spool, with the takeup on the left, so that
> may very well have been the case. Talk about the world's simplest
> tape drive: two spools and a multi-track (7 ??) head; one track had
> timing marks, so it didn't matter whether the tape was at a constant
> speed or not; blocks of (I think) 1K 12-bit words with an address
> header, so they could be read or written in either direction. I still
In the case of DECtapes, blocks were 129 words. I don't know the
block size typically used on LINCtapes.