comp.lsi.cad Frequently Asked Questions With Answers (Part 3/4) [LONG]

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- 1 schematic page (unlimited hierarchy)
- up to 25 parts on a page
- A-size page only
- up to 20 user-defined symbols
- no printing from within the Symbol Editor
- no export/import of symbols
- number of Symbol Library files that can be loaded is limited
to the total number shipped plus one

Netlister limitations include:

- up to 70 real devices for PSpice A/D netlists
- up to 50 symbols, before packaging, for PCB layout netlists

The following files are needed (use password 'anonymous':
<URL:ftp://ftp.netcom.com/pub/mi/microsim/62wine.exe>
<URL:ftp://ftp.netcom.com/pub/mi/microsim/62plsyne.exe>
<URL:ftp://ftp.netcom.com/pub/mi/microsim/readme.txt>
<URL:ftp://ftp.netcom.com/pub/mi/microsim/train.txt>
<URL:ftp://ftp.netcom.com/pub/mi/microsim/tutor.exe>
<URL:ftp://ftp.netcom.com/pub/mi/microsim/win32s25.exe>

A version for windows is also available. Read
<URL:ftp://ftp.netcom.com/pub/mi/microsim/.message>

to determine the necessary files.

31: Esim:

A new version of the switch-level simulator ESIM that can handle CMOS
transmission gates is available through MUG, ftp ftp.mosis.edu
(128.9.0.32))

32: iSPLICE3, a mixed-mode simulator for MOS/Bipolar circuits

(from Xiaocun Xu <x...@uivlsi.csl.uiuc.edu>)

"iSPLICE3: A Mixed-Mode Simulator for MOS/Bipolar Circuits"

The iSPLICE3 program is the third version of the SPLICE mixed-mode simu-
lation program currently under development at the University of Illinois,
based on research work originally initiated at the University of Califor-
nia at Berkeley. A mixed-mode simulator allows the circuit designer to
intelligently tradeoff simulation accuracy for speed within the scope of
a single simulator. The circuit designer is permitted to represent dif-
ferent parts of the same circuit at different levels of abstraction and
the mixed-mode simulator combines the different representations, models
and signal types in one simulation and produces the desired results while
greatly reducing the overall run-time. Currently, the iSPLICE3 program
has electrical, logic and and switch-level timing simulation modes. The
electrical analysis is performed using Iterated Timing Analysis (ITA)
which is an accurate, event-driven, relaxation-based circuit simulation
technique. The transistor models include MOS level 1, MOS level 3, the
TI MOS model due to Yang and Chatterjee and a Bipolar transistor model
from SPICE2. Accurate switch-level simulation is performed using ELOGIC.
In this mode, a set of discrete voltage states are defined and the time
required to make a transition between two adjacent states is computed
using electrical information. The precision of the model can be adjusted
to suit the desired level of accuracy. For logic simulation, simple
gates such as inverters, nors, nands, etc. are available with fanout-
dependent delay models.

The program can be obtained from the University of Illinois by
writing to:

Prof. R. Saleh, RE: Splice Program
Coordinated Science Laboratory
University of Illinois,
Urbana, IL. 61801.

There is a $100 cost for the tape, documentation, userguide and handling
charges for university or academic requests. FTP access is free of
charge on uivlsi.csl.uiuc.edu. There is a $400 charge to companies for
the entire tape/documentation set but no charge for FTP access. Please
make checks payable to the University of Illinois. Please request either
a Sun-tape or a 1600bpi magnetic tape.

33: Watand:

(From Phil Munro <FC13...@ysub.ysu.edu>)

This posting will give the interested person some information about the
WATAND (WATerloo ANalysis and Design) circuit simulator. Watand was
introduced at the 16th Midwest Symposium on Circuit Theory (1973). In
spite of its lack of advertising, Watand still offers some advantages
when compared with other well known circuit simulators. For example it
is a *truly* interactive simulator; that is, one enters the "WATAND"
environment in which analyses and design can be run and rerun, values
changed, settings queried and changed, etc.

Watand uses piecewise-linear as its primary simulation; other methods
are optional. It has ten built-in analyses which include the standard
dc, ac, and transient analyses, and two post-processors (display and
discrete Fourier). Output may be in the form of printed tables; graphics
display includes Tektronix 40xx output. At YSU interactive helps are
also available.

Watand provides for the creation and use of user defined elements in
addition to its own good stock of 34 built-in elements plus 21 built-in
user defined elements. User defined analyses and post-processors can
also be written, and it includes a powerful macro facility.

As of June, 1992, sale of the Watand simulator was still being handled
by Mark O'Leavey, Waterloo Engineering Software, 22 King St. S., Suite
302, Waterloo, Ontario, CANADA, N2L 1C6, Fax: (519) 746-7931; Phone:
(519) 741-8097. At that time I was informed that it was available only
for DECStation and Sparcstation, although we are running it quite suc-
cessfully at YSU under the CMS operation system on an Amdahl mainframe.

Two new and helpful manuals are available for the simulator. They
should be available at the Youngstown State University Bookstore, Youngs-
town, OHio 44555: Their approximate cost should be $7 each:

"WATAND Users Manual," by Dr. Phil Munro, Youngstown State
University, April 1992, 233 pages, 10 chapters, 4 appendices,
index.

"WATAND Introduction and Examples," by Dr. Phil Munro, Youngstown
State Unversity, June 1992, 204 pages, 12 chapters, index.

Watand does *not* include digital simulation at this time, nor does it
have any transmission-line elements. A self-heating BJT model has been
developed and is proving useful. Monte Carlo statistical simulation is
possible with dc and ac analyses using macro based analyses which have
been developed at YSU.

34: Caltech VLSI CAD Tools:

(From John Lazzaro <laz...@cs.berkeley.edu>)

Caltech VLSI CAD Tool Distribution - The Chipmunk Tools

The software tools in the Chipmunk system perform a wide variety of
tasks: electronic circuit simulation and schematic capture, graphics
editing, and curve plotting, to name a few. The tools run under a wide
assortment of Unix environments, as well as OS/2. Major Chipmunk tools
include:

Log: A graphical environment for entering circuit schematics, and
for analog and digital circuit simulation.
View: A tool for manipulating and plotting data.
Until: A graphics editor.
Wol: A tool for creating integrated circuit layout.

In addition to these major tools, many smaller tools are part of the
Chipmunk system. For more information on Chipmunk, access the Web page:

http://www.pcmp.caltech.edu/chipmunk/

or anonymous FTP to pcmp.caltech.edu and get the file:

pub/chipmunk/README

Contact the maintainer, John Lazzaro (laz...@cs.berkeley.edu) if you
have problems accessing the distribution.

35: Switcap2 (Current version 1.1):

This is a switched capactor simulator. It is available from:

SWITCAP Distribution centre,
411 Low Memorial Library,
New York,
N.Y. 10027.

36: Test Software based on Abramovici Text:

(Contributed by Mel Breuer of the Univ. of Southern California)

Many faculty are using the text by Abramovici, Breuer, and Fried- man
entitled "Digital Systems Testing and Testable Design" in a class on
testing. They have expressed an interest to supplement their course
with software tools. At USC we have developed such a suite of tools.
They include a good value simulator, fault simulator, fault col-
lapsing module, and D-algorithm-based ATPG module for combinational
logic. The software has been specifi- cally designed to be easily
understood, modified and enhanced. The algorithms follow those described
in the text. The software can be run in many modes, such as one
module at a time, single step, interactively or as a batch process. Stu-
dents can use the software "as is" to study the operation of the
various algo- rithms, e.g. simulation of a latch using different delay
models. Also, simple programming projects can be given, such as
extend the simulator from a 3-valued system to a 5-valued system; or
change the D-algorithm so that it only does single path sensiti- zation.
There are literally over 50 interesting software enhancements
that can be made by changing only a small part of the code. The system
is written in C and runs on a SUN.

If you are currently using the Abramovici text and would like a copy
of this software, please send a message to Prof. Melvin Breuer at
m...@poisson.usc.edu.

37: Test Generation and Fault Simulation Software

(Contributed by Dr. Dong Ha of Virginia Tech)

Two automatic test pattern generators (ATPGs) and a fault simula- tor
for combinational circuits were developed at Virginia Tech, and the
source codes of the tools are now ready for public release.
ATLANTA is an ATPG for stuck-at faults. It is based on the FAN algorithm
and a parallel-pattern, single-fault propaga- tion technique. It
consists of optional sessions using random pattern testing, deterministic
test pattern generation and test compaction. SOPRANO is an ATPG for
stuck-open faults. The algo- rithm of SOPRANO is similar to ATLANTA
except two consecutive patterns are applied to detect a stuck-open
fault. FSIM is a parallel-pattern, single-fault simulator. All the
tools are written in C. The source codes are fully commented, and
README files contain user's manuals. Technical papers about the tools
were presented at DAC-90 and ITC-91. All three tools are free to univer-
sities. Companies are requested to make a contribution of $5000 but
will have free technical assistance. For detailed in- formation, con-
tact:

Dr. Dong Ha
Electrical Engineering
Virginia Tech
Blacksburg, VA 24061
TEL: 703-231-4942
FAX: 703-231-3362
ds...@vtvm1.cc.vt.edu

38: Olympus Synthesis System

(From Rajesh K. Gupta <rgu...@sirius.Stanford.EDU>)

Recently there have been several enquiries about the Olympus Synthesis
System. Here are answers to some commonly asked questions. For details
please send mail to "synt...@chronos.stanford.edu".

1. What is Olympus Synthesis System?

Olympus is a result of a continuing project on synthesis of digital cir-
cuits here at Stanford University. Currently, Olympus synthesis system
consists of a set of programs that perform synthesis tasks for synchro-
nous, non-pipelined circuits starting from a description in a hardware
description language, HardwareC.

The output of synthesis is a technology independent netlist of gates.
This netlist can be input to logic synthesis and technology mapping tools
within Olympus or to UC Berkeley's mis/sis. Current technology mapping in
Olympus is targeted for LSI logic standard cells and a set of PGA archi-
tectures: Actel and Xilinx.

2. How is Olympus distributed?

The source code and documentation for Olympus is distributed via ftp.

3. What are the system requirements for Olympus?

Olympus has been tested on following hardware platforms: mips, sparc,
hp9000s300, hp9000s800, hp9000s700, vax. All the programs in Olympus
come with a default menu-driven ASCII interface. There is also a graphi-
cal user interface, called "olympus", provided with the distribution.
This interface is written using Motif procedures.

You would need about 40 MBytes of disk space to extract and compile the
system.

4. How can I obtain a copy of Olympus?

Olympus is distributed free of charge by Stanford University. However,
it is not available via anonymous ftp. In order to obtain a copy please
send a mail to "oly...@chronos.stanford.edu" where an automatic-reply
mailer would send instructions for obtaining Olympus software.

39: OASIS logic synthesis

(From William R. Richards Jr. <rich...@mcnc.org>)

OASIS is a complete logic synthesis system based on the Logic3 HDL
develped at MCNC (unfortunately neither VHDL or Verilog compatible).
k...@mcnc.org is the person responsible for it. OASIS is available to US
universities for $500 and non-US universities for $600. Industrial
license is $3000.

40: T-SpiceTM (was CAzM), a Spice-like table-based analog circuit simulator

(From William R. Richards Jr. <rich...@mcnc.org>)

CAzM is a Spice-like table-based analog circuit simulator. It offers sig-
nificant performance advantages over other Berkeley Spice derivatives. It
is used fairly extensively in our design community. US university
license is $175, non-US $250. Commercial license is $800. It comes with
an X11- based signal viewing tool Sigview which is public domain and may
be anonymous ftp'd from mcnc.org. I am the primary contact for CAzM at
MCNC.

(Contact sa...@tanner.com)

The CAzM program that was developed and offered by MCNC, has been
licensed for distribution by Tanner Research, Inc. of Pasadena, CA and
all future product availability and support is available from Tanner
Research. The program as offered by Tanner Research is a commercial pro-
duct and is now named T-Spice. This Spice-like simulator offers table-
based model evaluations for fast simulation performance, as well as,
included analytical models for use with digital and analog circuits.
Improvements to the CAzM models have also been made. Tanner Research
offers an optional Advance Model Library of charged controlled models
that includes an accurate, physically-based MOSFET model that is continu-
ous over all transistor regions of operations (including subthreshold),
and scales to submicron channel lengths. User defined models of any cus-
tom component or circuit written in "C" can be readily linked to T-Spice
as a general n-terminal device. Pricing is $995 for the simulator and
$1,245 with the Advance Model Library and Waveform Viewer. Universities
are offered a 75% discount. A modeling and extraction service is also
provided by Tanner Research to generate functional or transistor level
circuit simulation models for user supplied devices. The extraction ser-
vice provides extracted model parameters for existing circuit simulation
models, such as SPICE models, Tanner's own charge controlled MOS models,
or user's proprietary models. In addition, software is available to aid
users in extracting model parameters in house. For more information con-
tact Bhushan Mudbhary at Tanner Research (bhushan @ tanner.com), phone
818-792-3000 and fax 818-792-0300.

41: Galaxy CAD, integrated environment for digital design for Macintosh

Thanks to Simon Leung <sle...@sun1.atitech.ca>

The Galaxy CAD System is an integrated environment for digital design and
for rapid prototyping of CAD tools and other software. The system
currently includes schematic capture and simulation of both low-level and
high-level digital designs and is being expanded to include physical
design tools. Galaxy runs on a number of 680X0 platforms, including the
Apple Macintosh, HP9000/3XX, Apollo Domain, and Atari ST. Others will be
added according to demand.

The Galaxy CAD System is an ideal environment for teaching digital
design. It has been used successfully for both introductory logic design
and computer design courses at Wisconsin. Some of the features of Galaxy
that make it suitable for education are:

1. Integrated multiple-window environment: All Galaxy tools run
concurrently in a multiple window environment. Copying data
from one window to another is simple. Any number of simulation
sessions can be active simultaneously.

2. Hierarchy: the schematic editor and simulator are both fully
hierarchical. Building hierarchical designs is simple, including
creating symbols for modules. The simulator is a true hierarchical
simulator: it does not require a time-consuming macro-expansion
step.

3. Integrated editing and simulation: Designs are edited and
simulated in the same environment. Simulation input and output
can be shown directly on schematics, allowing direct manipulation
of net values. Unlike other products, Galaxy does not require
modification of the schematic to insert "switch" and "light"
components. In addition, Galaxy allows display of bus values in
hexadecimal directly on schematics to simplify debugging of
high-level designs. Simulation I/O can also use waveforms,
text files, and tables.

4. Faults: Stuck-at faults can be introduced on the schematic
editor and simulated immediately without rebuilding the
simulation model. This provides an excellent way to display
the effects of faults.

5. Buses: Galaxy supports specification and simulation of bus
structures, including complex extractions, fanouts, and bit
reversal. Buses are specified by annotating nets with text.
For simulation, buses are kept intact so that multiple-bit
high-level components can be used. Galaxy includes a library
of register-transfer components suitable for high-level
computer design and simulation.

6. Alternate specification of designs: In addition to schematics,
Galaxy users can specify design modules using a textual HDL
(GHDL) and using hardware flowcharts and state diagrams. A
hierarchical design can mix these representations as desired.

7. High-quality PostScript output: Galaxy schematics are of excellent
quality. Gates are drawn according to standard practices, e.g.,
OR gates are drawn with the correct circular arcs and not ellipses.

8. Uniform user interface: Galaxy tools have the same user interface
on all platforms, reducing student learning curves. In fact,
the same tool OBJECT CODE runs on all platforms due to the unique
structure of Galaxy.

9. Adding new simulation primitives is straightforward.

10. No cost: Galaxy is available for free via anonymous FTP (Apple
Macintosh version). Other versions will be made available based
on demand.

Galaxy is also an excellent environment for rapid prototyping of new CAD
tools. By building on top of available resources, we have been able to
prototype new tools in days or weeks that would ordinarily have taken
months or years. For more information, send e-mail.

To obtain Galaxy CAD, connect to "ftp://eceserv0.ece.wisc.edu/pub/galaxy"
using FTP. Log in as "anonymous" with password "guest". Galaxy is in
directory "pub/galaxy". The file "README" in that directory gives
further instructions. Please register as a user by sending e-mail to
"bee...@engr.wisc.edu".

John F. Beetem
ECE Department
University of Wisconsin - Madison
Madison, WI 53706
USA
(608) 262-6229
bee...@engr.wisc.edu

42: WireC graphical/procedural system for schematic information

(From Larry McMurchie <la...@cs.washington.edu>)

WireC is a graphical specification language that combines schematics with
procedural constructs for describing complex microelectronic systems.
WireC allows the designer to choose the appropriate representation,
either graphical or procedural, at a fine-grain level depending on the
characteristics of the circuit being designed. Drawing traditional
schematic symbols and their interconnections provides fast intuitive
interaction with a circuit design while procedural constructs give the
power and flexibility to describe circuit structures algorithmically and
allow single descriptions to represent whole families of devices.

The procedural capability of WireC allows other CAD tools to be incor-
porated into the design system. For example, we have defined an inter-
face to the SIS logic synthesis system wherein the designer can represent
part of the system behaviorally. WireC invokes logic synthesis on these
components to produce a structural description that can be incorporated
into the rest of the design.

Libraries of devices defining a particular netlist output format may be
defined by the user. The libraries currently distributed with WireC
include a default CMOS gate library whose output is the SIM format. This
format can be simulated with COSMOS or IRSIM and compared against a cir-
cuit extracted from layout. This library also includes devices that
allow a behavioral description to be synthesized and mapped using MIS or
SIS and incorporated into a larger circuit.

Another library is the xnf library for designing systems with Xilinx
FPGAs. Written by Jackson Kong, Martine Schlag and Pak Chan of UCSC,
this library contains devices specific to the 2000 and 3000 series Xilinx
LCA's. In addition to drawing the devices explicitly, one can represent
parts of a circuit with equations and have these synthesized automati-
cally.

Currently in progress is a library of CMOS gates for Cascade Design
Automation's ChipCrafter product. WireC provides a mixed
schematic/procedural design frontend for ChipCrafter, which uses module
generation, timing analysis and place and route software to create a phy-
sical layout from the WireC design specification.

WireC was written by Larry McMurchie, Carl Ebeling, Zhanbing Wu and Ed
Tellman. We are interested in any libraries you may develop and will

provide a limited degree of support.

WireC requires an X-Windows compatible environment and a C++ compiler
such as Gnu G++ and AT&T CC. WireC is available via ftp on the Internet.
For details send mail to

la...@cs.washington.edu ebe...@cs.washington.edu

43: LateX circuit symbols for schematic generation

(From Adrian Johnstone <adr...@cs.rhbnc.ac.uk>)

A set of circuit schematic symbols are available for use in LaTeX picture
mode. The set includes all basic logic gates in four orientations, FETs,
power supply pins, transmission gates, capacitors, resistors and wiring
T-junctions. All pins are on a 1mm grid and the symbols are designed to
be easily used with Georg Horn's TeXcad program: we even supply you with
a palette picture file that displays all 52 symbols in a compact grid
that you can cut and paste from within TeXcad. Each symbol lives in its
own .mac file and is defined as a 'savebox' so as to reduce memory con-
sumption. You must add the [bezier] option to your 'documentstyle' com-
mand. A small manual is provided in both Postscript and .dvi forms.

The files lcircuit.zip and lcircuit.tar are available for anonymous ftp
from ftp://cscx.cs.rhbnc.ac.uk/pub/lcircuit (134.219.200.45). I will also
be uploading them to various ftp servers in the coming week.

44: Tanner Research Tools (Ledit and LVS)

(Contact sa...@tanner.com)

Low cost, yet very powerful commercial ASIC design tools are available
from Tanner Research, Inc. in Pasadena, CA. These products are used by
industry and universities alike. Tanner's products are nominally priced
at $995 per program, with a combined package named L-Edit Pro available
for $3,495 on the PC. Universities are offered a 75% discount. Here is
a list of their current programs:

L-EditTM : A full-custom layout editor with CIF and GDSII
input/output. Features a 32-bit coordinate space,
all-angle geometry, unlimited hierarchy and number
of layers. The L-Edit Pro package includes L-Edit/DRC
for design rule checking, L-Edit/SPR for automatic
standard cell placement and routing, L-Edit/Extract
for extracting transistors, capacitors, resistors and
generic devices for SPICE-level simulation or comparison
to a schematic and LVS ,a netlist comparison tool for
topological and parametrical verification. Optional
layout libraries are also available.

T-Spice: Circuit level simulator (See item 41 for detail

GateSimTM : Gate-level simulator. A full array of technology mapping
libraries are also available.

Products are available for the PC, Macintosh, Sun and Hp UNIX platforms.
For more information contact Bhushan Mudbhary at Tanner Research (bhushan
@ tanner.com), phone 818-792-3000 and fax 818-792-0300.

45: SIMIC, a full-featured logic verification simulator.

(From comp.archives.msdos.announce)

SIMIC is a full-featured logic verification simulator. It has been
demonstrated that SIMIC can uncover a number of critical design errors
that other simulators miss. SIMIC has shown superior accuracy and
throughput when compared to competitive products. Here are some of
SIMIC's important features:

- Mixed-mode simulation allows the free intermixture of true
bilateral switches (ideal and resistive), gate, plus functional level
built-in and user defined primitives.

- A wide variety of output, whose detail, content and format are, to
large extent, user defined.

- A large repetoire of simulation options and controls that can be
applied interactively, or in batch operation, and simplify
trouble-shooting of your design.

- Automated Test equipment emulation, allows debugging test programs
using SIMIC troubleshooting techniques.

- Sophisticated hazard analysis including: Spike, Pulse, Conflict,
Oscillation, Setup, Hold, Pulse-width, Near (what-if)
detection, among others. Hazard propagation is also supported.

The student version of SIMIC is limited to a maximum of 500 elements
(parts). In all other respects it is the same program as the commercial
offering. The PC student version requires a 386 or better and at least 2
Meg of memory. Both a DPMI and a VCPI version are included in the pack-
age. Both versions require EMS *NOT* be disabled. SIMIC is also avail-
able on Sun and other platforms.

The latest version is 1.02.00. The changes from revision 1.00.04 are:

Bug Fixes:
- Rams properly handled by circuit compiler.
- BTG (Ideal switches) compiled correctly with dynamic delays.
- By-name pin connections accepted by circuit compiler.
- JK Flip-flop timing checks can now be disabled.
Enhancements:
- Reduction in storage requirements for small RAMS.
- Fault Sensitization analysis added.
- Fault Simulation and grading added.

This revision can be taken from ftp://oak.oakland.edu/pub/msdos/electric,
or ftp://wuarchive.wustl.edu/systems/msdos/electric . The files in ques-
tion are sim120bn.zip (Simic logic and fault simulator plus examples) and
sim120dc.zip (Simic Engineering and User's Guides).

The latest version is:
<URL:ftp://ftp.njcc.com/pub/genashor/simoc/msdos/simic.zip>

46: LASI CAD System, IC and device layout for IBM compatibles

(from Mike Fitsimmons <mi...@eceuil.ece.uiuc.edu>)

I have uploaded to SimTel, the Coast to Coast Software Repository (tm),
(available by anonymous ftp from the primary mirror site OAK.Oakland.Edu
and its mirrors):

SimTel/msdos/cad/
lasi442a.zip LASI v4.4.2 IC layout CAD pgm; unzip in
lasi442b.zip LASI v4.4.2 IC layout CAD pgm; unzip in
lasi442c.zip LASI v4.4.2 IC layout CAD pgm; unzip in

This is Version 4.4.2 of the LASI CAD System that has been released
expressly for Internet by Dr. Dave Boyce the author. LASI was developed
to do integrated circuit and device layout on almost any IBM compatible
personal computer. It may be used for other CAD applications such as
schematics or printed circuit boards. Drawings may be translated into
GDSII, CIF or HP-GL. It is a CAD system that is easy to learn and run,
and is primarily intended for educational use in schools and colleges by
students, researchers, or anyone who doesn't have time of funding for
more elaborate CAD systems.

Changes: This version contains many improvements to LASI itself, the HP-
GL plotter, the CIF converter and other programs.

The condensed files are in three zipped files LASI442A.ZIP, LASI442B.ZIP
and LASI442C.ZIP. You must have all three zipped files to have a complete
set of LASI files.

Uploaded on behalf of the author.

47: EEDRAW, an electrical/electronic diagramming tool for IBM compatibles

This is available from SimTel mirror sites such as:

<ftp://oak.oakland.edu/SimTel/msdos/graphics/eedraw24.zip>

This is the 2.4 release of EEDRAW, an electrical/electronic diagramming
tool for the IBM PC. Electrical Engineering drawing (with layers).
Please read the readme file in the primary archive for information on
other source programs needed such as the Libary files.

48: MagiCAD, GaAs Gate Array Design through MOSIS

(from Tom Smit <smith....@mayo.edu>)

MagiCAD is a system for GaAs semi-custom design through MOSIS and elec-
tromagnetic modeling of digital interconnect.

MagiCAD is now available on the following platforms:
* DEC Alpha workstation running OSF/1 2.0
* HP 9000/700-series workstation running HP-UX 9.05
* Sun SparcStation running Solaris 2.3 (SunOS 5.3)

The Mayo Graphical Integrated Computer Aided Design (MagiCAD) system
package provides a comprehensive design environment for the development
of digital systems, from initial concept to post-layout verification of
integrated circuits (ICs). MagiCAD focuses on the development of high-
speed Gallium Arsenide (GaAs) gate array designs. Specialized elec-
tromagnetic simulation tools are provided to address high clock rate
issues such as crosstalk and reflections, which become more important as
clock rates exceed several hundred MHz or signal edge rates become less
than 500 pico-seconds. MagiCAD provides all the necessary tools for high
clock rate GaAs IC design, and is also integrated with non-Mayo circuit,
logic, and fault simulators.

MagiCAD provides a lower risk approach than full-custom design for
universities wishing to perform digital GaAs design through MOSIS. This
is done by providing a gate array design environment where low-level
transistor design and layout issues have already been solved and
abstracted into a technology library of pre-defined cells. This frees the
student or researcher to solve the still challenging tasks of system and
gate-level design and layout to get high clock rate chips fabricated
through MOSIS that meet all specifications.

MagiCAD has been used in the design of many GaAs chips that have been
successfully fabricated. The MagiCAD electromagnetic modeling tools have
been used in the analysis of many actual packages, multi-chip modules
(MCMs), and printed circuit boards (PCBs), uncovering and avoiding prob-
lems that are commonly associated with high-frequency, fast edge-rate
designs. The Vitesse Fury (TM) GaAs VSC2K gate array is provided as a
MagiCAD technology library, and has been used for both graduate and
undergraduate student chip designs. The Vitesse FX20K (HGaAs-III) has
been entered as a MagiCAD technology library, as a replacement for the
VSC2K (HGaAs-II). A Mayo FX20K chip design is in fabrication now, and
after it is tested, the FX20K technology will be released for student
designs through MOSIS by 2Q 1995.

Functionality that has been integrated into MagiCAD includes:
o Vitesse Fury VSC2K GaAs gate array technology library (HGaAs-II)
o Database which integrates all tools
o Schematic entry through a general purpose graphics editor
o Circuit simulator
o Logic and timing simulators
o Fault grading
o Place and route tools
o Layout verification tools
o Output to standard GDSII format for mask creation
o Electromagnetic analysis
- Cross section entry with graphics editor
- Multilayer multiconductor transmission line (MMTL) modeling
- Network tool for solving cases with many transmission line components
- Lossy and non-lossy cases
- Frequency and time domain result displays
- Used for analyzing complex design paths, through chip, MCM, and PCB

The Advanced Research Projects Agency (ARPA) has funded Mayo to supply
MagiCAD to universities in the USA for research and educational purposes.
The direct cost to the universities for the MagiCAD software itself is
zero (although there may be costs for any non-Mayo software that univer-
sities may want). Mayo-supplied MagiCAD training and support costs to
these institutions is funded by ARPA, and is therefore free to the
universities in the USA. MagiCAD is not being distributed or supported
outside the USA.

The general steps for a university to begin using MagiCAD
for digital GaAs gate array design include:
1) Contact Mayo Foundation to acquire MagiCAD software
and GaAs technology libraries.
2) Contact MOSIS to acquire general MOSIS information
and Vitesse-specific GaAs technology information.

Point Of Contact For Acquiring MagiCAD And MagiCAD Support:

Tom Smith
Mayo Foundation
Special Purpose Processor Development Group
200 First St. S. W., Guggenheim 1016A
Rochester, Minnesota 55905
Telephone: (507) 284-0840
Telefax: (507) 284-9171
EMail: Smith....@Mayo.Edu

Point Of Contact For Acquiring General MOSIS Information And Vitesse-
specific GaAs Technology Information:

Sam Reynolds
The MOSIS Service
USC/ISI
4676 Admiralty Way
Marina del Rey, CA 90292-6695
Telephone: (310) 822-1511 x172
Telefax: (310) 823-5624
EMail: sdrey...@mosis.edu

49: XSPICE, extended version of Spice

(from Jeff Murray <jm...@hydra.gatech.edu>)

I am one of the developers of XSPICE, and at the risk of being deluged
with requests for specific information on the tools, I can volunteer to
answer at least some questions. Currently there is no ftp site for infor-
mation; if there were, this posting would likely be unnecessary. However,
we are prohibited from posting even the User's Manual due to technology
export restrictions.

The following is a copy of the original press release on XSPICE. If
anyone would like additional clarification beyond this, or if some
aspects of the release are unclear, we can certainly take this as an
opportunity to remedy the situation. Please note that at the current time
there are many dozens of individuals who have obtained a copy of the
tools; if they have any comments or observations to make, I'm sure they
would be most welcome to other members of the user community.

XSPICE Press Release

January 2, 1993

Georgia Tech Research Corporation

XSPICE, introduced at the 1992 International Symposium on Circuits and
Systems (ISCAS), is an extended and enhanced version of the popular SPICE
analog circuit simulation program originally developed at the University
of California at Berkeley. XSPICE was developed at the Georgia Tech
Research Institute (GTRI) as a tool for simulating circuits and systems
at multiple levels of abstraction. XSPICE permits a user to simulate ana-
log, digital, and even non-electronic designs from the circuit level
through the system level in a single simulator. A special Code Modeling
feature allows users to add new models directly into the simulator exe-
cutable for maximum simulation speed and accuracy. Code models are writ-
ten in the C programming language allowing arbitrarily complex behavior
to be described. Code model development tools are provided to simplify
the process of creating new models, compiling them, and linking them with
the XSPICE core.

XSPICE provides a rich set of predefined code models in addition to the
standard discrete device models available in SPICE. The XSPICE code model
library contains over 40 new functional blocks including summers, multi-
pliers, integrators, magnetics models, limiters, S-domain transfer func-
tions, digital gates, digital storage elements, and a generalized digital
state-machine.

Digital functions are simulated in XSPICE through an embedded event-
driven algorithm added to the SPICE core. This algorithm is coordinated
with the analog simulation algorithm to provide fast and accurate simula-
tion of mixed-signal circuits and systems. The event-driven algorithm
supports a new "User-Defined Node" capability allowing additional event-
driven data types to be defined and used. XSPICE comes with a 12-state
digital data type as well as a user-defined node library that includes
'real' and 'integer' types useful in simulating sampled-data systems such
as Digital Signal Processing algorithms.

XSPICE is currently available for UNIX workstations and is supplied in
source code form allowing users to customize and extend the simulator and
models to particular needs. To date, the simulator has been successfully
compiled and used on HP Apollo and Sun workstations. The XSPICE simulator
and User's Manual are available with a cost-free license arrangement from
the Georgia Tech Research Corporation for a distribution charge of US
$200 (including first class postage within the U.S.A.; an additional US
$25 is required for overseas delivery by air). For further information,
please contact the Office of Technology Licensing, Georgia Tech Research
Corporation, Georgia Institute of Technology, 400 Tenth Street, Atlanta,
GA 30332-0415, USA, or phone (404) 894-6287 (voice) or (404) 894-9728
(FAX). Internet users may send email to XSP...@GTRI.GATECH.EDU to obtain
copies of the order form and license agreement (please include the word
"license" in the subject header when mailing to this address).

50: MISIM, a model-independent circuit simulation tool

(from Bardo Muller <ba...@ief-paris-sud.fr>)

University of Washington has recently released the updated MISIM simula-
tor. The new release (Sun version) is now available through ftp with
anonymous login. The node address is 128.95.31.10. The release is under
/pub/misim.SUN.2.3.a. If you have any question, please don't hesitate to
contact us (misim_...@ee.washington.edu). Or, you can contact Prof.
Andrew Yang at 206-543-2932.

Attention:
---------

We are currently re-writing the whole MISIM system in C with broader
design consideration. The noise and temperature simulation capability
will be incorporated into our next release. It would have more flexible
front end with better simulation performance. The new version is
expected sometime around the end of this summer. Since the actual
release no longer reflected the level of our technology, we removed it
from our ftp directory.

MISIM Development Team
Department of Electrical Engineering
University of Washington

MISIM 2.3A Release: General Information
------------------------------------------

A) New capabilities:
----------------

MISIM 2.3A is distinguishable from the previous release in that is now
integrates a transistor-level mixed analog-digital simulator based on
analytical digital macromodeling. The mixed-signal simulator is equipped
with a front-end translator which accepts standard SPICE netlist syntax
and converts it into MISIM mixed-mode syntax. Analytic macromodels for
digital subcircuits are generated and loaded into MISIM core simulator
automatically. Synchronized simulation is then performed for the digital
subcircuits (processed by analytic solution) and the analog subcircuits
(processed by proven analog simulation algorithms) with much accelerated
speed and superior analog accuracy ( within 3-5 % of SPICE).

The MISIM mixed-signal simulator supports all standard Berkeley MOS model
(Level 1, 2, 3, BSIM 1, BSIM 2). User-defined MOS models of arbitrary
complexity are also supported.

Currently, the procedure of processing analytic digital macromodeling
cannot be applied to bipolar devices (G-P model). Hence, all bipolar
transistors will be simulated as "analog" components.

MISIM's X-window graphic environment, WISE, has been upgraded to support
the mixed-signal simulation capabilities.

B) Model Improvements:
------------------

MISIM 2.3A now supports improved SPICE models (MOS, Diode, BJT). Many of
the model discontinuities have been resolved leading to more reliable
simulation. The MOS Level 2 and Level 3 models have also been upgraded to
an improved charge-conserved models. The standard SPICE diode model has
been enhanced to a non-quasi-static model capable of simulating accu-
rately the diode recovery effect.

These improved SPICE models are released as linked models. Users are not
recommeded to unload these improved models.

C) A New Parser:
------------

MISIM 2.3A incorporates a new netlist parser which supports two different
modes:

1) Standard SPICE netlist syntax - default mode. 2) Enhanced SPICE net-
list syntax - MISIM mode.

This new capability is designed to make MISIM completely spice-
compatible. In addition, the new parser now handles symbolic names and
expressions.

D) Updated Documentations:
----------------------

An updated MISIM User's guide is available in postcript form. On-line
documentations is also provided.

E) Future Release (MISIM 3.0):
--------------------------

1) The next release will include a new C-version analog simulator which
has been benchmarked to be a factor of 2 to 3 times faster than the
current fortran version.

2) The mixed-signal simulator will be enhanced to improve digital cover-
age rate (percentage of a mixed A/D circuit which can be processed by the
analytic digital macromodel) for better simulation performance.

51: Nelsis Cad Framework

(from their 'README' file)

Release 4.3 is the latest version of the Nelsis IC Design System. It
contains a CAD framework that puts a substantial added-value under the
fingertips of the designer by organizing the design information and
keeping track of the design evolution. It permits integration of
tools of different origin and achieves run-time efficiency. The
framework is based on intelligent management of meta data on top of
the actual design descriptions; it administers high level information
about the design activities and the structure and status of the design,
rather than operating at the level of the detailed design descriptions.

The framework services, such as flow management, version manage-
ment, concurrency control and state management, have been implemented
on top of the meta data management module. The framework controls
access to the design objects and administers meta data by performing
OTO-D queries. Tools operate on top of the framework via the Data
Management Interface, obtaining access to the design data according to a
nested transaction schema.

The Nelsis CAD Framework is available, together with a set of design
tools for demonstration purposes, through anonymous ftp from
<URL:ftp://dutente.et.tudelft.nl/pub/nelsis> .

Release 4.6.1 is now available. More information on NELSIS can be found
on WWW at <URL:http://www.ddtc.dimes.tudelft.nl/docs-4.6/docs.html>

52: APLAC, a general purpose circuit simulation and design tool

(from Sakari Aaltonen <sak...@picea.hut.fi>)

-----------------------------------------
APLAC 6.2
-----------------------------------------

General information

APLAC, a program for circuit simulation and analysis, is a joint develop-
ment of the Circuit Theory Lab of Helsinki University of Technology and
Nokia Corporation's Research Center. The main analysis modes are DC, AC,
noise, transient, oscillator, and (multitone harmonic) steady state.
APLAC can also be used for measurements with IEEE-488 apparatus. APLAC's
transient analysis uses convolution for correct treatment of components
with frequency-dependent characteristics. Monte Carlo analysis is avail-
able in all basic analysis modes, as is sensitivity analysis in DC and AC
modes. N-port Z, Y, and S parameters, as well as two-port H parameters,
can be used in AC analysis. APLAC also includes a versatile collection of
system level blocks for the simulation and design of analog and digital
communication systems.

Component models

Too many to be listed here. In addition to familiar Spice models, a great
number of microwave components (microstrip/stripline) are included. Sys-
tem models include formula-based and discrete-time models useful in RF
design. The model parameters of the components may have any functional
dependency on frequency, time, temperature, or any other parameter. Users
can create new components by defining their - possibly nonlinear - static
and dynamic characteristics in APLAC's interpreter-type language. Spice-
syntax models can be imported.

Input

APLAC reads its input - the nodes, branches, and model parameters of the
components - from a text file. Model libraries can be created and
included. Expressions are written in a program-like manner; user func-
tions may be defined. Conditional and looping control structures are sup-
ported.

Output

The output results from one or several sweeps of any user-defined func-
tion of the circuit parameters, time, frequency, or temperature. The
results may be printed or plotted in rectangular or polar coordinates, or
on the Smith chart. Graphics output can be directed to an HPGL- or CSDF-
type file, or to a graphics file for later viewing.

Optimization

APLAC includes several optimization methods: gradient, conjugate gra-
dient, minmax, random, simulated annealing, tuning (manual optimization)
and gravity center (design centering). Any parameter in a design problem
can be used as a variable and any user-defined function may act as an
objective.

Machine environment

Michael Altarriba

unread,
Jan 10, 1997, 3:00:00 AM1/10/97
to

Archive-name: lsi-cad-faq/part4


Unix: X11; PC: MS-Windows (math coprocessor required).

Contact information
-------------------
Martti Valtonen Heikki Rekonen
Helsinki University of Technology Nokia Research Center
Circuit Theory Laboratory Hardware Design Technology
Otakaari 5A, SF-02150 Espoo, FINLAND P.O.Box 156, SF-02101 Espoo,
FINLAND
Fax: 358-0-460224 Tel: 358-0-43761
e-mail:mar...@aplac.hut.fi Fax: 358-0-455 2557

A WWW server is available at
<URL:http://picea.hut.fi/aplac/main.html>, and an experimental
hypertext tutorial is at
<URL:http://picea.hut.fi/aplac/tutorial/main.html>

Free (university version) binaries for HP9000/700, Sun4, and PC machines
are available via FTP from ftp://nic.funet.fi/pub/cae/aplac . Help files,
PS manuals, and collections of APLAC examples are in the same directory.

53: SLS, a switch-level simulator

(from comp.lsi.cad)

DELFT UNIVERSITY OFFERS UNIQUE SWITCH-LEVEL SIMULATOR

SLS is a switch-level simulator that can be used to simulate the logic
and timing behavior of large digital circuits that are described at the
(mixed) MOS transistor, gate and functional level. It has fast and accu-
rate algorithms to predict the timing behavior of MOS circuits containing
> 100,000 transistors. MOS transistor-level circuit descriptions are
easily mixed with gate-level and functional-level circuit descriptions,
where the behavior of the latter are described in the C programming
language. There is an X-window based user-interface to graphically edit
the input signals and to inspect the simulation output signals. The same
interface is used to alternatively simulate the circuit with the well-
known circuit simulator SPICE. SLS has already been used by many people
at many different sites, and numerous chips have been designed with it.
SLS is now made available world-wide to serve as a useful design and
verification tool to the international design community. Apart from
being used as a stand-alone tool, SLS can also be used as a part of the
popular design system for Sea-Of-Gates circuits OCEAN, or it can be con-
nected to the advanced Nelsis CAD framework.

The SLS simulator has three different simulation levels:

1. Purely logic simulation based on abstract transistor strengths:
This level more or less behaves similar to the original switch-level
model as proposed by R.E. Bryant. It computes logic states by
only considering node states and transistor types.

2. Logic simulation based on exact transistor dimensions and node
capacitances: This level uses resistance division and capacitance
division algorithms to compute logic states. It finds correct logic
states in much more situations than conventional switch-level
simulators, e.g. when a resistance division occurs between a saturated
transistor and a non-saturated transistor.

3. Logic and timing simulation based on transistor and node parameters:
RC time constant evaluations are used to approximate real voltages by
PIECEWISE-LINEAR VOLTAGE WAVEFORMS. This not only provides delay times
for the circuit, but is also delivers an accurate representation for
transient effects like spikes and races.

Apart from electrical network elements like MOS transistors, resistors
and capacitors, an SLS network may contain (i) gate primitives like
inverters, nands, nors, etc. and (ii) user-defined function blocks like
roms, shiftregisters, multipliers. The behavior of function blocks is
described by the user in the C programming language: it is specified by
the user how the values of the output terminals and the state variables
are computed from the values of the input terminals and the state vari-
ables.

For more information about SLS, see,

"Switch-level timing simulation," P.M. Dewilde, A.J. van Genderen,
A.C. de Graaf, Proc. ICCAD 85 Conf., Santa Clara, Nov. 1985,
pp. 182-184

"SLS: An Efficient Switch-Level Timing Simulator Using Min-Max Voltage
waveforms," A.J. van Genderen, Proc. VLSI 89 Conf., Munich, Aug. 1989,
pp. 79-88.

"SLS: Switch-Level Simulator User's Manual," A.C. de Graaf, A.J. van
Genderen, Delft University of Technology (available for ftp at the
address below).

Availability:

SLS is written in C and runs under UNIX and X-windows. It runs, among
other things, on Sun SPARC stations, HP 9000 series 700/800 machines, and
PCs running Linux. The program is available for free under the terms of
the GNU General Public License. It can be retrieved via anonymous ftp
from ftp://dutentb.et.tudelft.nl/pub/sls .

It is also possible to obtain SLS as a part of the OCEAN system for the
design of Sea-Of-Gates circuits. This system can be obtained from on
ftp://donau.et.tudelft.nl/pub/ocean . The OCEAN system among other
things contains a layout-to-circuit extractor that can extract large lay-
outs and that stores the result directly in the database that is read by
SLS. Furthermore, SLS is available as a tool in the Nelsis CAD framework
from the directory pub/nelsis on dutente.et.tudelft.nl. The latest ver-
sion of SLS can always be found on dutentb.et.tudelft.nl .

For questions, remarks and bug reports, contact

Arjan van Genderen
Delft University of Technology
Department of Electrical Engineering
Mekelweg 4 phone: 31-15-786258
2628 CD Delft fax: 31-15-623271
The Netherlands email: ar...@dutentb.et.tudelft.nl

54: OCEAN, a sea-of-gates design system

(from Patrick Groeneveld <oc...@donau.et.tudelft.nl>)

About OCEAN: the sea-of-gates design system
-------------------------------------------

OCEAN is a comprehensive chip design package which was developed at Delft
University of Technology, the Netherlands. It includes a full set of
powerful tools for the synthesis and verification of semi-custom sea-of-
gates and gate-array chips. OCEAN covers the back-end of the design tra-
jectory: from circuit level, down to layout and a working chip. In a nut-
shell, OCEAN has the following features:

+ Available for free, including all source code.
+ Short learning curve making it suitable for student design courses.
+ Hierarchical (full-custom-like) layout style on sea-of-gates.
+ Powerful tools for placement, routing, simulation and extraction.
+ Any combination of automatic and interactive manual layout.
+ OCEAN can handle even the largest designs.
+ Running on popular HP, Sun and 386/486 PC machines, easy
installation.
+ Includes three sea-of-gates images with libraries and a
200,000 transistor sea-of-gates chip.
+ Can be easily adapted to arbitrary images with any number of layers.
+ Interface programs for other tools and systems (SIS, cadence, etc.)
+ Robust and 'combat-proven', used by hundreds of people.

How to retrieve OCEAN and additional documentation?
---------------------------------------------------

The entire OCEAN system is available for free via anonymous ftp, gopher
or on tape. A powerful installation script is included, so you can get
started very quickly without hacking up the code. You can retrieve OCEAN
and additional documentation via:

anonymous ftp: <URL:ftp:donau.et.tudelft.nl:pub/ocean>
gopher: olt.et.tudelft.nl (port 70) or use the path
World --> Europe --> Netherlands -->
Delft University of Technology Electronic Engineering
--> Research activities -->
The OCEAN sea-of-gates Design System

We advise to retrieve first the documents with the user manual. (The file
'ocean_docs.tar.gz'). If you have any questions, remarks or problems,
just contact us:

Patrick Groeneveld or Paul Stravers
Electronic Engineering Group, Electrical Engineering Faculty
Delft University of Technology
Mekelweg 4, 2628 CD Delft The Netherlands
Phone: +31-15786240 Fax: +31-15786190
Email: oc...@donau.et.tudelft.nl

55: ALLIANCE, a CAD package and simulator for teaching digital VLSI design

--- (from Frederic PETROT <fr...@cao-vlsi.ibp.fr>)

******************************************************
* ANNOUNCEMENT OF ALLIANCE RELEASE 3.0 May 10th 95 *
******************************************************

The release 3.0 of the public domain ALLIANCE VLSI/CAD system is
now available at:

ftp.ibp.fr [132.227.60.2] in /ibp/softs/masi/alliance

CONTENT

ALLIANCE is a complete set of CAD tools and portable libraries for
research and education in digital VLSI design. The ALLIANCE CAD system
has been developed at the MASI laboratory (Universite Pierre et Marie
Curie, Paris France). It includes a VHDL compiler and simulator, logic
synthesis tools, automatic place and route, DRC, extractor, functional
abstraction and formal proof tools etc... All the ALLIANCE cell
libraries use a symbolic layout approach in order to provide pro-
cess independence: Cmos process from 1.6 micron to 0.8 micron have been
successfully targetted.

Several new tools have been introduced into release 3.0, (...and several
bugs have been fixed)

1) FPGA synthesis
The logic synthesis tool ALLIGATOR is dedicated to fast prototyp-
ing on XILINX FPGAs. The input description uses the same VHDL
subset as the ASIMUT VHDL simulator.

2) Floor-plan router
The high performance floor-plan router CHEOPS, developped by BULL
is part of this release. This toll uses the same symbolic layout
approach as all the ALLIANCE portable libraries. It as been used
for multi-millions transistors circuits. Only the binary code
for SPARC is available.

3) Timing analysis
The ALLIANCE design-flow separates functionnal verification (us-
ing zero delay VHDL models) and the timing verification. The
timing analyser TAS takes an extracted, transistor level net-list
(ALLIANCE or SPICE format) as input, and provides all relevant
timing information.

INSTALLATION

ALLIANCE is totally free, under the terms of the GNU General Pub- lic
License. It includes C source files and on-line English do- cumentation
(UNIX man)

1) A hierarchical makefile allows each ALLIANCE tool to be com-
piled and installed separately. The disk space required to
compile and install the full ALLIANCE package is about 150
megs.

2) The release 3.0 has been successfully compiled with K&R cc and
GNU gcc compilers. The full alliance package can now run on
SPARC, LINUX and DEC architectures.

TUTORIALS

The release ALLIANCE 3.0 contains six separate tutorials:

1/ ADDACCU
The design of a very simple chip (adder/accumulator) to get
started with the ALLIANCE tools (about 500 transistors).

2/ AMD2901
The design of the 4 bits AMD2901 processor, from the VHDL spe-
cification to the GDSII layout, using the ALLIANCE portable
standard cell library (about 3000 transistors).

3/ DLX
The design of the 32 bits DLX microprocessor (HENNESSY & PAT-
TERSON) from the VHDL specification to the GDSII layout, using
the ALLIANCE data-path compiler and logic synthesis tools
(about 30000 transistors).

4/ FPGA
The synthesis of a simple circuit on Xilinx FPGA (Field Prog-
rammable Gate Array). The produced cirucit uses 20 CLBs.

5/ Synthesis Tools
Different levels of synthesis and optimization (Finite State
Machine synthesis, logic synthesis, logic and net-list optimi-
zations) are covered by this tutorial.

6/ Data Path
Building simple data paths using the data path compiler FPGEN
and the data path router DPR.

56: ceBox EDIF Viewer and Schematic Generator

<from comp.archives>

A free demo version of the ceBox EDIF Viewer is now available from the
the following site:

ftp://www.concept.de/nview

you find the following files:

README 3k

nlview-2.5-sun.tar.gz 856k for SPARC SunOS4+5
nlview-2.5-hp.tar.gz 1168k for HP-PA
nlview-2.5-win32.zip 536k for Windows95+WindowsNT
doc-2.5-sun.tar.gz 88k Documentation
doc-2.5-hp.tar.gz 88k Documentation
doc-2.5-win32.zip 89k Documentation

The *ceBox EDIF Viewer* displays schematic pages and symbols of any
EDIF 200 (level 0) file. It is an easy-to-use tool to analyse EDIF
schematic and EDIF netlist files.

The *ceBox EDIF Kit* is a programming library to bundle C++ user func-
tions to the Viewer and to build standalone EDIF processors. The Kit's
in-core data base allows to access/modify all EDIF data.

A free demo version of nlview (schematic generation and viewing tool) for
SPARCstation is available via anonymous ftp from:

ftp://ftp.Germany.EU.net/shop/concept-engineering/nlview
[192.76.144.75]

The tool reads EDIF 200 netlist files or structural Verilog files,
creates schematics and displays them on screen. Some extra functions are:

+ cross-probing between schematic and ASCII file

+ searching objects by name (using wild-cards)

+ highlighting critical pathes (infos from separate file)

+ writing EDIF 200 schematic and PostScript files

For more information, please contact:

Concept Engineering
Burkheimer Str. 10
D-79111 Freiburg, Germany

Tel: ..49-761-473099
Fax: ..49-761-441063
email: in...@concept.de

57: Analog CMOS VLSI Design Educational Resource Kit

(from MUG)

UMass Dartmouth is pleased to announce the release of Version 1 of the
Analog CMOS VLSI Design Educational Resource Kit. Version 1 of the
Resource Kit may be obtained via anonymous ftp at the site

micron.ece.umassd.edu

The release includes the following files and information:

The CIF file for a 2 micron Mosis Tinychip using p-well technology; and
manuals containing five tutorials based on the chip set.

These circuits were used in an undergraduate course on analog VLSI design
during the spring semester at the University of Massachusetts Dartmouth.
They are also being currently used in a graduate level course in analog
VLSI design. The students in the undergraduate course had a single
introductory digital VLSI design course as background, and were familiar
with MAGIC, SPICE and CAzM, a SPICE-like circuit simulator.

If you have any comments, corrections or suggestions regarding the
release, or ideas for other circuits that you have found useful in your
classes and that could be incorporated in later releases, please feel
free to contact me. Good luck!

Robert H. Caverly, Ph.D.
ECE Department
University of Massachusetts Dartmouth
N. Dartmouth, MA 02747
cav...@micron.ece.umassd.edu
(508) 999-8474

58: TDX Fault Simulation and Test Generation Software

(from Dan Holt <d...@attest.com>)

TDX Fault Simulation and Test Generation Software

Free demo/student copies of Attest Software's fault simulation, Iddq,
DFT, and automatic test pattern generation tools are available by
anonymous ftp.

This software is fully functional on any circuit with less than 200
gate-level primitives. It is also fully functional on the GL85 micropro-
cessor circuit (about 3000 primitives) which is included with the suite
of tools. General-use licenses can be provided free to accredited univer-
sities for non-commercial, educational purposes.

The software is built around a high-performance concurrent fault simula-
tor that is accurate on a wide-range of state and timing sensitive cir-
cuits. It supports synchronous and asynchronous designs containing logic
gates, MOS transistors, tri-state buffers, flip-flops, single/multi-port
RAMs, complex bus resolution functions, and Verilog User Defined Primi-
tives (UDPs). The software also supports the detailed pin timing and
strobing features found on "tester-per-pin" automatic test equipment. The
software supports Verilog and VHDL netlists.

The GL85 microprocessor, which is a clone of the once-popular 8085
microprocessor, is a fully functional model for which three views are
provided: behavioral, RTL, and gate level. Using this clone, a tutorial
shows the user how to achieve improved controllability and/or observabil-
ity for his or her circuit, resulting in improved fault coverage, some-
times with very little additional time or effort expended in the design
cycle. The tutorial was written by Dr. Alex Miczo.

The software is available by ftp at:

<URL:ftp://ftp.attest.com/pub/attest>

The README contains installation instructions, and identifies the loca-
tion of the GL85 models and the postscript tutorial. The web page is:

<URL:http://www.attest.com/>

For more information, please contact:

Attest Software Inc.
47100 Bayside Parkway
Fremont CA 94538-9942 USA

(510) 623-4253 voice
(510) 623-4550 fax

in...@attest.com

59: Nascent Technologies CDROM - magic and spice releases for Linux

The Linux from Nascent CDROM, Version 1.0, is only $39.95 plus shipping
and handling, and comes with an 30-day unconditional money-back guaran-
tee. If you aren't completely satisfied, return the package with your
receipt within 30 days and the purchase price, excluding shipping and
handling, will be refunded to you.

In addition, Nascent offers the Linux from Nascent Plus package for only
$89.95, which includeds six months of email support and a 30% discount
off a future release of the CDROM with your CDROM purchase.

Nascent Technology
811 Haverhill Drive
Sunnyvale CA 94087 USA
Tel: (408) 737-9500
Fax: (408) 241-9390
Email: nas...@netcom.com

Linux is a freely distributable Unix(R) compatible operating system for
the IBM(R) 386/486 PC and compatibles written by Linus Torvalds from the
University of Helsinki, Finland. It was developed by a unique world-wide
collaboration of programmers over the internet, and is covered by the GNU
General Public License. Linux is a modern, high performance network
operating system, much like ones used for years on engineering and pro-
fessional workstations.

The Linux from Nascent CDROM is an entirely new distribution of the Linux
operating system, and includes over 400 mbytes of source code, binaries,
and documentation for Linux and applications. The Linux from Nascent
distribution features:

* 52 page User Guide
* automated root, swap, and package installation from CDROM
* simple user account and network administration scripts
* Linux 0.99.14 plus net-2 networking
* extensive online documentation and manuals
* network printer support
* X Window System(TM)
* OpenLook(TM) 3d window manager
* SCSI disk and tape support
* TeX(TM) and ghostscript word processor and viewer
* Ingres database management
* GNU C compiler and utilities
* GNU emacs, vi clone text editors
* sound and graphics support
* Over 100 high resolution images translated from Kodak PhotoCD(TM)
* magic and spice electronic design tools
* GNU Chess, Shogi, pooltable, xpilot, flight simulator, ...

60: Time Crafter 1.0, a timing diagram documentation tool

(from Rick Burgett <bur...@csips1.nrlssc.navy.mil>)

I have uploaded to the SimTel Software Repository (available by anonymous


ftp from the primary mirror site

ftp://OAK.Oakland.Edu/pub/msdos/electric/timecrft.zip and its mirrors):
timecrft.zip WIN3: Electronic ckt timing diagram generator

Time Crafter Version 1.0 is a timing diagram documentation tool. A tim-
ing diagram is used by electrical engineers and technicians to document
the way a circuit or system operates or should operate. This type of
documentation is crucial to good design and debugging but up to now one
could only use paper and pencil (with a good eraser) or an expensive CAD
package costing $1000 or more to produce these diagrams on a PC. Time
Crafter has features that make it easy to document and update a circuit
design of any complexity.

Time Crafter is Microsoft Windows based to provide a simple yet powerful
user interface which is device independent.

Special requirements: Windows 3.x

61: ACS, a general purpose mixed analog and digital circuit simulator

(from comp.lsi.cad)

A new version of ACS (Al's Circuit Simulator) has been posted to
alt.sources. It is also available by ftp from ftp://cs.rit.edu/pub/acs
or ftp://ee.rochester.edu/pub/acs . If you don't have net access you
can get it by dial-up from (USA) 716-272-1645.

ACS is a general purpose mixed analog and digital circuit simulator. It
performs nonlinear dc and transient analyses, fourier analysis, and ac
analysis linearized at an operating point. At this point the analog is
stronger than the digital. (In fact, the digital part is rather weak.)
It is fully interactive and command driven. It can also be run in batch
mode or as a server. The output is produced as it simulates. Spice com-
patible models for the MOSFET (level 1 and 2) and diode are included in
this release.

This version (0.13) includes several improvements including real Fourier
analysis and better time step control based on truncation error. There
are other minor improvements.

Since it is fully interactive, it is possible to make changes and re-
simulate quickly. The interactive design makes it well suited to the
typical iterative design process used it optimizing a circuit design. It
is also well suited to undergraduate teaching where Spice in batch mode
can be quite intimidating. This version, while still officially in beta
test, should be stable enough for basic undergraduate teaching and
courses in MOS design, but not for bipolar design.

In batch mode it is mostly Spice compatible, so it is often possible to
use the same file for both ACS and Spice.

The analog simulation is based on traditional nodal analysis with itera-
tion by Newton's method and LU decomposition. An event queue and incre-
mental matrix update speed up the solution for large circuits.

It also has digital devices for true mixed mode simulation. The digital
devices may be implemented as either analog subcircuits or as true digi-
tal models. The simulator will automatically determine which to use.
Networks of digital devices are simulated as digital, with no conversions
to analog between gates. This results in digital circuits being simu-
lated faster than on a typical analog simulator, even with behavioral
models. The digital mode is experimental and needs work. There will be
substantial improvements in future releases.

The source and documentation can be obtained by anonymous ftp from
ftp://ee.rochester.edu/pub/acs or ftp://cs.rit.edu/pub/acs . It can also
be obtained by dial-up (USA) 716-272-1645 in /pub/acs. It may be distri-
buted under the terms of the GNU general public license. The dial-up
also has some test circuits, pre-compiled executables for Next, Sun4,
MSDOS and possibly others, and documentation in dvi and postscript.

62: LOG/iC, a logic synthesis package for PLDs

(from Ralph Remme <R...@ns.isdata.de>)

LOG/iC EVAL
- - ISDATA GmbH Karlsruhe, Germany / ISDATA Inc. Oakland CA
- - FSM and logic synthesis for programmable logic devices
- - Several output formats: JEDEC, POF, HEX, EDIF, XNF, Open-PLA,
PALASM, ...
- - PLD data base as an electronic reference
- - PC Windows
- - free version of LOG/iC PLUS for educational and research use only
- - anonymous ftp: ftp://gate.fzi.de/pub/ISDATA (141.21.4.3)
- - email: isd...@isdata.de

ISDATA GmbH ISDATA Inc.
Daimlerstrasse 51 P.O. Box 19278
D-76185 KARLSRUHE Oakland, CA 94619
GERMANY U.S.A.
Phone:(+49) 721 75 10 87 Phone: (++1) 510 5318553
FAX: (+49) 721 75 26 34 Fax: (++1) 510 5318417
Mr. Peter Bauer Mr. Paul Hoy

An evaluation copy of LOG/iC2 is available:

LOG/iC2 EVAL
- ISDATA, Germany
- Logic synthesis and simulation for PLDs 16V8, 20V8 and 22V10 from all
manufacturers
- Input: Hierarchical entry supported by the graphical hierarchy
editor, high level description language, 74xx library,
macrogenerator
- Output: Programming file (JEDEC)
- includes the PLD data base, an electronic reference manual
- Functional simulator
- PC version for Win 3.1 and Win 95
- CD can be ordered free of charge at ISDATA via email: isd...@isdata.de

The full version of LOG/iC2 supports CPLDs from nearly all vendors,
FPGAs from Xilinx and Actel, and all Simple PLDs.
It offers timing simulation and as an option VHDL entry.

63: SIMLAB, a circuit simulation environment

(from Bardo Muller <ba...@ief-paris-sud.fr>)

Simlab is a circuit simulation environment consisting of a flexible,
user-friendly front-end operating in conjunction with a sophisticated and
versatile simulation engine. The program is written in C and is specifi-
cally designed to be used as an educational tool and as a research plat-
form. Simlab can be operated in either batch or interactive mode. An
optimized version for the Connection Machine (cmvsim) is available.

The user is allowed to separately specify algorithms for the various
aspects of the simulation. These include:

Simulation environment (e.g. serial or parallel depending on
the underlying hardware).
ODE system solution (e.g. point)
ODE system time integration (e.g. backward-Euler, trapezoidal,
second-order Gear),
Nonlinear algebraic system solution (e.g. multidimensional
Newton's method, nonlinear relaxation),
Linear system solution (e.g. sparse Gaussian
elimination, Gauss-Jacobi relaxation, conjugate gradient,
conjugate gradient squared),

Furthermore, simlab has a notion of simulation mode and different methods
can be specified for different modes. At present, supported modes are DC
for the calculation of operating points, and Transient for the calcula-
tion of the time response of a circuit. For instance, assuming that the
user has specified the multidimensional Newton's method for solving the
nonlinear system of equations, the linear solver associated could be dif-
ferent depending of what type of simulation is being performed.

In its basic form, simlab is a powerful circuit simulator, but it is also
designed to be easily customized for research purposes. For example, sim-
lab forms the core of special-purpose simulation programs, such as a
switched capacitor filter simulator and a simulator for vision circuits.
The program code is highly modular, so that researchers can easily con-
struct and test algorithms by inserting them into the existing simlab
framework.

Simlab can be obtained from ftp://rle-vlsi.mit.edu/pub/simlab. Question
or problems related to the installation or usage of the simlab circuit
simulator should be addressed to sim...@rle-vlsi.mit.edu (18.62.0.214).
Any bugs should be reported to simla...@rle-vlsi.mit.edu .

64: Pcb, an X-based PC board design tool

(from comp.windows.x.apps)

Pcb is a handy tool for the X Window System build to design printed cir-
cuit boards. It supports multiple layers and circuit libraries with a
resolution of 0.001 inch. Refer to the manual for more details.

The new feature are:

- user interface has been 'cleaned up'
- number of key strokes have been reduced by menues
- encapsulated PostScript is now supported
- all deleted objects can be recovered
- most of the operations can also work with 'selected' objects
- some circuits and packages are included
- fileselect boxes with user defined commands and preset directories
make a flexible user interface
- the position of element names is now changeable. Both names of an
element are changeable
- grid settings are either absolute (to 0,0) or relative to the
position where it has changed
- messages and stderr of external commands can be redirected to a
log window

- *** a special goodie: ***
a functional demo layout with a Motorola 68HC11 microcontroller
and LCD display

ftp servers (ftp.funet.fi thanks to Matti Aarnio):
ftp://ftp.medizin.uni-ulm.de/pub/pcb-1.2
ftp.funet.fi:/pub/???

Please have a look at the README files before getting the preformated
documentation.

There is also a mailing list to share knowledge, libraries and other
information (without too much traffic right now):
p...@pluto.medizin.uni-ulm.de to reach all members
pcb-r...@pluto.medizin.uni-ulm.de to subscribe or unsubscribe
owne...@pluto.medizin.uni-ulm.de for problems with the list
Thoma...@medizin.uni-ulm.de to reach the author only

65: SPICE-PAC, A Modular Spice Simulator with Enhancements

(from Bardo Muller <bardo....@ief-paris-sud.fr>)

SPICE-PAC - A Modular Spice Simulator with Enhancements

Author: W.M. Zuberek
Computer Science Department
Memorial University of Newfoundland
St. John's, Nfld, Canada A1C-5S7
tel. (709) 737-4701 or 737-8627
fax: (709) 737-2009

SPICE-PAC is a mature simulation package that is, with only a few minor
exceptions, upward compatible with the popular SPICE-2G circuit simulator
but provides a number of extensions.

SPICE-PAC allows the construction of interactive applications in which
circuit simulation can be combined with different optimization methods,
statistical analysis, symbolic simulation. High-level (behavioral) simu-
lation is possible by user-defined functions and tables.

The SPICE-PAC Fortran/C-source (version 94.08) can be found in the direc-
tory ftp://ftp.cs.mun.ca/pub/sppac

66: U.C. Berkeley Low-Power Cell Library

(from Tom Burd <bu...@eecs.berkeley.edu>)

**********************************************************************

======================================================================
U.C. Berkeley Low-Power Cell Library
======================================================================
FOR CONDITIONS OF USE, PLEASE READ THE ACCOMPANYING COPYRIGHT FILE

Overview:
--------

This Library is based on the Mosis (<URL:http://www.mosis.edu>) SCMOS
Design Rules and has been implemented via the Magic 6 layout editor. The
sdl files and oct facets provided allow the Library to be used within the
LagerIV silicon compilation system
(<URL:ftp://infopad.eecs.berkeley.edu/pub/lager>). Also, symbols,
schematics, and vhdl files are provided for using the library within the
Powerview (Trademark of Viewlogic Systems, Inc.) design environment. The
documentation at present is available in postscript form as well as in
FrameMaker 4 (Trademark of Frame Technology Corp.) format. These are
denoted as .ps and .doc files.

This library has been used in the development of over a dozen chips here
at U.C. Berkeley as of Dec. 1994, so it has been through several rounds
of beta testing already.

Since the library is naturally partioned by the type of cell, I have set
up separate distributions for each partition:

1. TimLagerlp Array tiled cells. (e.g. sram, fifo, etc.)
2. dpplp Bitsliced cells for datapath construction.
3. stdcell2_3lp Standard Cell Library.
4. pads1_0clp 1.0um pads.
5. pads1_2clp 1.2um pads.

Updates to the Library will be by the above partitions, such that each
partition will have an associated version number.

PLEASE SEND BUG-REPORTS TO bu...@eecs.berkeley.edu AND PREFIX THE SUBJECT
LINE WITH "LPLIB BUG:" FOR EASIER ACCOUNTING.

PLEASE DO NOT DIRECT INQUIRES REGARDING HOW TO USE LAGERIV,
POWERVIEW(TM), OR FRAMEMAKER(TM) TO MYSELF, BUT RATHER TO AN APPROPRIATE
NEWS GROUP DISCUSSION.

======================================================================
Installation:
-------------

1. Untar the desired partitions in an installation directory (denoted
as LPLIB)

2. To use with LagerIV, I have also included a "lager" file here to
be used, that will function properly if the LPLIB environment
variable is set.

======================================================================
Documentation:
-------------

1. Documentation is provided within each library. Not all docs, mainly
the timing, may be completed. However, all schematics and required
parameters are given/described. The timing characterizations that
are done are for either MOSIS's 1.2um (HP) run (TimLagerlp, pads1_2clp,
stdcell2_3lp), or the same process but with shifted VT's (dpplp).
This was achieved by shifting the flat-band voltage, and used purely
for research and not fabrication/testing purposes. The MOSIS 1.0um
(HP's "0.8um" process, but really, lambda=0.5) parameters were used
for the pads1_0clp library. The process parameters used is noted in
the docs.

2. Spice Files: I have included here the 1.2um and 1.0um spice files used
for
the timing. All delays are measured 50%-50%. The BSIM models
for used and simulated with HSPICE (Trademark Meta Software).

3. You can also refer to my thesis for further overview of the design
choices made, and an overview of the Library:

<URL:http://infopad.eecs.berkeley.edu/~burd/gpp/gpp.html#masters>
<URL:ftp://infopad.eecs.berkeley.edu/pub/burd/masters.ps>

67: The Substrate Resistance Extractor SUBSPACE

(from ar...@cas.et.tudelft.nl (Arjan van Genderen))

We have made available for anonymous FTP a program for computing sub-
strate resistances, called SUBSPACE. The program is based on the paper
"Extraction of Circuit Models for Substrate Cross-Talk", by T. Smedes,
N.P. van der Meijs and A.J. van Genderen, Proceedings ICCAD 1995.

The program uses as input a geometrical description of a set of contacts
defined on top of a semi-conducting substrate. This input is generated
using an X-window based graphical layout editor. The properties of the
substrate and the parameters for the boundary-element method that is used
to compute the substrate resistances, are specified in a parameter file.
Effects of chip side-walls can also be included. The output consists of
a SPICE resistance network.

SUBSPACE is a special version of the layout-to-circuit extractor SPACE;
everything that SUBSPACE can, SPACE can do too. Moreover, SPACE can
simultaneously extract MOS and bipolar transistors, RC models and 3D
capacitances. Actually, the only special thing about SUBSPACE are the
technology files and a pre-configured set of options. The full version
of SPACE will be released in several weeks.

The program SUBSPACE is available in executable form, including documen-
tation, for HP 700/800 computers and Sun Sparc stations. It can be
obtained via anonymous FTP from
ftp://dutentb.et.tudelft.nl/pub/space/subspace, or via the WWW address
specified below.

For more information, see our WWW page:
http://dutentb.et.tudelft.nl/research/space.html

A tutorial is found at
http://dutentb.et.tudelft.nl/research/subspace.html

68: XRLCAD, A C++ library for manipulating Calma (GDS) and CIF libraries

(from Mumit Khan <kh...@xraylith.wisc.edu>)

XRLCAD -- CXrL CAD toolset

This package contains a C++ class library to manipulate Structure (as in
Calma/CIF) hierarchies. There is also loaders for CIF and Calma, as well
as output drivers for these formats. A bunch of demo programs are
included which I wrote when I was testing the library, and these programs
turned out be quite useful tools.

The library is still in its infancy, but it's reasonably solid; in a few
months I'll take another look at it and probably overhaul it.

Core directory organization: relative to $TOPDIR

./xrutils - standard stuff (lists, stacks, hash tables, strings)
./xrcad - C++ class libraries for manipulating cell libraries
and the embedded structure hierarchy
./calma - input/output drivers for Calma/GDS
./cif - input/output drivers for CIF
./technology - very incomplete. Started to see if I could do what
Magic does with CIF layers <--> GDS layer ids.

Demo programs: relative to $TOPDIR

./gdsflatten - flatten a GDS file
./gdsxtract - extract cell hierarchy (and specific layers)
./gdshier - show hierarchy
./gdsinfo - useful info (hierarchy, bounding box)
./cifflatten - flatten a CIF file (and extract specific layers)
./cif2gds -
./gds2cif -
./biaser - mask compensation program
./gdsclip - clip and extract an area of a layout

I've successfully built a recent snapshot on the following platforms:

sparc-sunos-4.1.3: SC2.0.1, Cfront-3.0.1, GCC-2.6.3
sparc-sunos-5: SC2.0.1, GCC-2.6.3
rs6000-aix-3.2: Cfront-3.0.1, GCC-2.6.3
decstation-ultrix4.2: Cfront-3.0.1, GCC-2.6.3
(and I think it worked!)

If you use this package, please do send an email to
<kh...@xraylith.wisc.edu> so I can send you info as new enhancements and
releases become available.

Further information is available at

<URL:http://www.xraylith.wisc.edu/~khan/software/xrlcad/xrlcad.html>

%-----------------------------------------------------------------%
Mumit Khan kh...@xraylith.wisc.edu
Research Staff Phone: +1 608 265 6075
Center for X-ray Lithography FAX: +1 608 265 3811
University of Wisconsin-Madison http://www.xraylith.wisc.edu/~khan/
%-----------------------------------------------------------------%

69: SAVANT, an Analyzer of VHDL Applications for Next-Generation Technology

(From jp...@el.wpafb.af.mil (Paul Jarusiewic Jr.))

Extracted from <URL:http://www.ece.uc.edu~paw/quest>:

The primary goal of SAVANT (Standard Analyzer of VHDL Applications for
Next-Generation Technology) is to stimulate research among the VHDL com-
munity by providing an extensible, object-oriented, well-documented
intermediate form (IF) and a freely available analyzer to convert VHDL
into the IF. Because the IF analyzer is released in source form, the
additional derived classes can be inserted into the C++ class hierarchy.
Thus, user actions can benefit fully from the fact that the IF is
object-oriented. Consequently, no procedural interface is provided or
needed.

70: Protel Demos for Windows

Demos of Advanced Schematic 2.3 for Windows, Advanced PCB 2.5 for Windows
and Protel-Easytrax (DOS Freeware) are available for download from
www.protel.com, or ftp.protel.com.

Advanced PCB 2.5 Disk 1 in zip form
Advanced PCB 2.5 Disk 2 in zip form

Advanced Schematic 2.3 Disk 1 in zip form
Advanced Schematic 2.3 Disk 2 in zip form

Easytrax (DOS Freeware) in zip form (this is a fully-working program)

Autotrax Demo (DOS) in zip form

Special Limited Edition Demo Pack

Complete the Request form and our Sales department will send qualified
applicants the current Limited Edition Protel Design System demo package.
This demo pack features the special Limited Edition of Advanced PCB. The
Limited Edition version allows you to create and save actual PCB layouts
with up to 20 components and 200 connections. This special version also
includes a descriptive tutorial booklet which discusses features of these
tools. Because these tools are very easy to use, many users will be able
to demo the products with the aid of the packages' comprehensive On-line
Help systems.

Note: If the desired service is not currently available, please e-mail
your request to sale...@protel.com or seek assistance from any of the
available Protel contacts in your country.

71: BPECS PCB Software

(from bstp...@connectnet.com <Steve Rabin>)

Our new PCB Software BPECS version 1.06 features:

Automatic path from schematics to placement to layout
Improved autorouter
Postscript AND Gerber output
Camera ready art from Windows print device
Pseudo-Teardrop pads for reduced trace breakage
Design your own SMD packages w. mixed coordinates
FREE 30 day evaluation - all features availible
FREE upgrades and accessories from our web-site
Low $295 price
1 year limited warranty

Visit our website to download your copy.

------------------------------------------------------------
Best Proto (TM) * http://www.bestproto.com/ftpsite
Prototyping Boards * CAD Software * Engineering Services
Box 232440, San Diego, CA 92193-2440 * (619) 286-9000 ph/fax
------------------------------------------------------------

72: RF, an RF Circuit Simulation Tool

(from Academic Technologies <acad...@onthenet.com.au>)

Analog and RF Circuit Simulation and Tool for Engineers, Radio Amateurs,
Hobby and Students or anyone interested in linear circuit analysis and
design.

RF has been written as a design aid for the radio amateur, hobbyist, stu-
dent or practicing engineer. The primary aim is as tool for radio fre-
quency design, however the program is suitable for use in any analog
design. Pulse response and DC circuits are encompassed in this version
however it is not intended as a replacement or alternative to programs
such as SPICE rather as an addition to the existing tools available. It
is particularly aimed at high frequency small signal design using S
parameters.

RF runs under Windows 3.1, Windows 95 and Windows NT


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