SRAM transistor sizing
Aditya Agrawal
in a simple CMOS 6-transistor/cell SRAM ?
SPecifically, I have seen SRAM cells designed by other people
with the size of the P pullup in the ramcell as WP=2.0,LP=3.7
in a 1.0um technology. I would have thought that LP should
have been 1.0um to keep the size of the ramcell as small as
possible.
Also, how can we figure out what size the row select and
column select transistors need to be for a particular sized
RAM for optimal area ?
I would appreciate any information on this.
Thanks
Aditya
Robert Groover
>What are the criteria that one should use when sizing transistors
>in a simple CMOS 6-transistor/cell SRAM ?
Look in the literature for discussions of "beta" in SRAM cells - the
sizing ratio between driver and pass transistors turns out to be important
for jointly optimizing speed, size, and stability.
>SPecifically, I have seen SRAM cells designed by other people
>with the size of the P pullup in the ramcell as WP=2.0,LP=3.7
>in a 1.0um technology. I would have thought that LP should
>have been 1.0um to keep the size of the ramcell as small as
>possible.
I think the longer PMOS serves to limit crowbar current when the latch is
switching - also I think that 6T SRAM latches are usually sized so that the
NMOS drivers are quite dominant. (You don't need strong drivers on both
pull-up and pull-down sides - you just set up your bitline sensing to see
which side is getting pulled down.)
Hopefully someone MUCH more knowledgeable can give you a much more
informative reply, but perhaps the foregoing will be of some use.
Robert Groover gro...@netcom.com (PGP key on request)
Member ECS, AVS, ACM, OSA, Sen.Mem.IEEE, Reg'd Patent Atty
Mark Johnson
>>What are the criteria that one should use when sizing transistors
>>in a simple CMOS 6-transistor/cell SRAM ?
>>with the size of the P pullup in the ramcell as WP=2.0,LP=3.7
>>in a 1.0um technology. I would have thought that LP should
>>have been 1.0um to keep the size of the ramcell as small as
>>possible.
>>
>I think the longer PMOS serves to limit crowbar current
>when the latch is switching - also I think that 6T SRAM
>latches are usually sized so that the NMOS drivers are
>quite dominant.
False, and True.
There are 3 transistor sizes to choose in a 6T CMOS SRAM cell:
The PMOS pullup size, the NMOS pulldown size, and the NMOS
access transistor (also called "passgate") size. There are
two identical copies of each transistor, giving a total of
six. (Iconoclasts, who design the cell with nonidentical
transistor sizes between the left half and the right half
of the flipflop, need read no further).
Luckily for the designer, one of them is pretty much a
don't care: the PMOS. Over a very broad range of PMOS
sizes, the memory cell works just fine. Remember that
the PMOS has an extremely easy job: supply enough current
to overcome junction leakage in the cell. This is so easy
that some designs completely _remove_ the PMOS and replace
it with a ten-GigaOhm poly resistor! (giving the 4T+2R
cell). Remember that one of the goals is to make your cell
layout as small as possible. So start with PMOS W/L =
min/min. Then if there's room available (i.e. if it doesn't
increase the cell layout area), increase the PMOS L as
much as possible. This will increase the capacitance
on the flipflop nodes (helps protect against soft errors a
little), and will make the cell slightly easier to write.
But if you have to stick with W=min, L=min, rest easy.
Lots of your predecessors have successfully built SRAMS
this way.
The very complicated problem is to choose the NMOS
access transistor's size (the passgate). First difficulty
is to choose an L. You'd like it to be minimum, BUT remember
that a column of n SRAM bits (say, n=256 or more) has
have n of these access transistors hanging on it. If
they "leak" just a little bit [and remember these suckers
are sitting in the absolutely worst case condition of
VDS=VDD so Drain Induced Barrier Lowering decreases their
threshold voltage], the leakage is multiplied by n.
So the "off" bitline, which you _think_ should be sitting
at V(bitline_pullup), is actually pulled down by this
leakage, and your bitline high-level is lower than you
thought. So the bitline delta-V that you get during a
read, is smaller than you thought.
Perhaps catastrophically so.
If you believe your transistors are not-very-leaky, then
it's safe allow yourself to try L_passate = Lmin in
the experiments that follow. If not, don't try an
L_passgate smaller than, say, 1.3*Lmin.
Now, leakage aside, there are just three other factors
that affect the transistor sizes of the two NMOS's.
They are
1. Cell Stability
2. Speed
3. Layout Area
Cell Stability is a DC phenomenon. It's just a measure
of the cell's ability to retain its data when you're
not wrting, and to change its data when you are.
Recall that a cell reads by tugging down one of its
bitlines (against the bitline pullup). Also recall
that you write a cell by tugging down one of its
bitlines. So, what's the difference between a read
and a write? (Why doesn't the act of reading, also
write the cell?)
The answer is, the bitline moves a different amount
in a read than it does in a write. In a read, the
bitline only moves a little, and this isn't enough
to "flip" the cell. Whereas in a write, the bitline
moves a lot, and this is enough to "flip" the cell.
And the designer is responsible for arranging things
so "a little", "a lot", and "enough" all work together.
Do this experiment: Simulate your memory cell along with
its bitline pullups. Start off with the cell storing
a "one". Now, raise the wordline. And very very slowly,
begin to pull current out of bitline-true (i.e do a
write but extremely slowly.) Find the bitline voltage
at which the cell "flips" from "one" to "zero".
Call that bitline voltage the "cell trip point".
Define a quantity called ReadMargin. ReadMargin is
(bitline voltage during a read) minus (cell trip
point). Suppose you've read a cell containing a
zero, and now you read a new cell (you assert a new
wordline) that contains a one. You don't want the
previous read data on the bitlines, to write the
new cell. So you want the bitline-low voltage that
results from a read, to be comfortably above the
cell trip point.
Define another quantity called WriteMargin. WriteMargin
is (cell trip point) minus (bitline low voltage during
a write). You want the series connection of your
write drive transistors + column I/O transistors, to
be able to pull down the bitline (fighting against
the bitline pullup) low enough to actually write the
cell. You want the bitline-low voltage during a write,
to be comfortably below the cell trip point.
Usually it's considered optimum if you design your cell
so that ReadMargin=WriteMargin. That is, you've got
about the same margin of safety during reads as you've
got during writes.
And what determines ReadMargin and WriteMargin?
ASSUMING you've got well-designed bitline pullups
and a well-designed write path (column I/O and
write driver), the Margins are determined by a
ratio [can you see why?]:
memcell NMOS pulldown W/L
Cell Ratio = ----------------------------
memcell NMOS passgate W/L
Do some SPICE simulations; try every Cell Ratio
from 0.25 to 5.0 in steps of 0.25. See which one
is closest to the optimum (ReadMargin = WriteMargin).
There's a well known optimum value of CellRatio in
industry, but it's more instructive if you figure
it out yourself by experimentation. OF COURSE
you'll be doing simulations at two different VDD's
(specmin and specmax), two different junction
temperatures (specmin and specmax), and four
different fab processing skews (ss, ff, sf, fs),
for a total of 304 simulations. {19 different cell
ratios, times two VDD's, times two TJ's, times four
process skews}. Sorry gang, this is how industrial
strength design actually happens. Get used to it.
So now you know the Cell Ratio you need for optimum
Cell Stability. What takes you from this ratio,
to individual device sizes?
First is speed. If there were no such thing as
junction capacitance and gate overlap capacitance,
you'd want your access transistor (passgate) to be
infinitely big. Then it'd he able to pull
infinitely large currents out of the bitline, and
therefore infinitely fast during a read. SADLY
there is such a thing as parasitic capacitance, and
whatever the bitline capacitance is of one cell,
it's multiplied by the number of cells on a bitline.
So you'll have to try several different passgate
sizes and see which one gives the best (highest)
ratio of (read current) / (bitline capacitance).
And let's not forget wordline capacitance. The
bigger the passgate in the memory cell, the more
capacitive loading it places on the wordline. So
you may improve the bitline speed (via whopping
big access transistors) but ruin the wordline speed.
Try it and see.
Second is layout area. You gotta lay out the
bohunkin large transistors that SPICE tells you
are wonderful. What works in layout? Do a
comparison: lay out a cell with passgate W/L=
min/min, with NMOS pulldown W/L = (CellRatio*min)/min,
and with PMOS W/L=min/min. This is the smallest
possible cell that is optimally stable. Now lay
out your cell using the passgate W/L and pulldown
W/L that SPICE tells you is wonderful. Compare the
areas. Are you happy? If not, "interpolate"
between these two memory cells and try again.
Several folks have done Ph.D. theses in which they
write CAD tools that automatically size transistors
for arrays of SRAM cells, and then do the polygon
layout. Generally these are known as "SRAM macro
generators" or "RAM compilers". You could take a
look.
Also you could read every paper ever written in
the IEEE Journal of Solid State Circuits, by two
influential authors:
Stephen Flannigan
Barbara Chappell
(Don't worry; there are only three or four papers
total. And you only have to go back as far as
1982 or so, when CMOS SRAM started to take off.)
See what the literature has to say about cell sizing.
Remember, though, that _your_ fab process is probably
a lot different from the fab process these authors
used (at Motorola and IBM, respectively).
[Hint: there's an Author Index in the back of
the December issue, every year].
Best of luck,
--- Mark Johnson
Rajesh Gupta
>
> What are the criteria that one should use when sizing transistors
> in a simple CMOS 6-transistor/cell SRAM ?
>
> SPecifically, I have seen SRAM cells designed by other people
> with the size of the P pullup in the ramcell as WP=2.0,LP=3.7
> in a 1.0um technology. I would have thought that LP should
> have been 1.0um to keep the size of the ramcell as small as
> possible.
>
> column select transistors need to be for a particular sized
> RAM for optimal area ?
>
> I would appreciate any information on this.
>
>
> Thanks
> Aditya
>
Typically, the conductance of pull downs is about three times that
of the pass gates, in order to ensure that cell storage is not
overwritten during read. The pass transistor conductance is,
in turn, several times that of the pull up, to ensure cell overwrite
during write. Since the pass gates add to the cell select drivers,
there is an incentive to make these small. The net effect is
that often the mobility difference between n and p (which narrows
with decreasing channel length) is often not sufficient to create
a weak enough pull up from minimum transistor size. Depending upon
how the cell is laid out, usually it is possible to increase the pull
up channel length (which is often perpendicular to the pull down
channel) since the corresponding dimension is limited by pull down
channel widths and spacing rules.
Rajesh Gupta rgu...@cs.uiuc.edu
tomar....@gmail.com
I am bit confused for the read margin definition by Mark Johnson
>>Define a quantity called ReadMargin. ReadMargin is
>>(bitline voltage during a read) minus (cell trip
>>point). Suppose you've read a cell containing a
>>zero, and now you read a new cell (you assert a new
>>wordline) that contains a one. You don't want the
>>previous read data on the bitlines, to write the
>>new cell. So you want the bitline-low voltage that
>>results from a read, to be comfortably above the
>>cell trip point.
If we are considering the precharge was inadequate or If there is failure to precharge in between successive read 0's on it will keep lowering the voltage of BL. This would not work.
So what is the significance of such Read margin definition?
Please clarify.
nainasin...@gmail.com
> What are the criteria that one should use when sizing transistors
> in a simple CMOS 6-transistor/cell SRAM ?
>
> SPecifically, I have seen SRAM cells designed by other people
> with the size of the P pullup in the ramcell as WP=2.0,LP=3.7
> in a 1.0um technology. I would have thought that LP should
> have been 1.0um to keep the size of the ramcell as small as
> possible.
>
> Also, how can we figure out what size the row select and
> column select transistors need to be for a particular sized
> RAM for optimal area ?
>
> I would appreciate any information on this.
>
>
> Thanks
> Aditya
I am designing a SRAM for my project
For a single 6T cell, during reading how to store data bit in cell so that we can read it. Should i push data externally using a supply to read it?
I am having trouble in understanding reading and writing cycle of SRAM using cadence virtuso.
Thanks
Naina