FPGA Express & VHDL files

[V Ram]

Hello.

I am using FPGA Express 3.0 to synthesize some VHDL. I have segmented my
design into multiple blocks (entity&arch pair) each of which resides in a
separate VHDL file.

If I used ModelSIM to simulate, I can make a "top-level" file and
instantiate "components" which are really the modules I designed. I use a
package to describe the modules and a custom library to hold the modules
and then in the top-level I use the library/components and tie it all
together with signals.

However, I cannot get FPGA Express to understand this, even if I create a
components library that matches my name and compile the smaller parts into
this library. Any suggestions? Any easier way to do a top-level file where
I simply connect blocks together? (Graphically)?

Thanks,
V. Ram.

[Kent Orthner]

V Ram <ipickledth...@mrbourns.com> writes:
> I am using FPGA Express 3.0 to synthesize some VHDL. I have segmented my
> design into multiple blocks (entity&arch pair) each of which resides in a
> separate VHDL file.
>
> If I used ModelSIM to simulate, I can make a "top-level" file and
> instantiate "components" which are really the modules I designed. I use a
> package to describe the modules and a custom library to hold the modules
> and then in the top-level I use the library/components and tie it all
> together with signals.

There should be no problem doing what you're trying to do with Express;
having a top-level entity in a VHDL file, and instantiating your sub-modules.

I think that your problem may be the way that you're using libraries; try
simply removing the library definitions, and compiling all your files as
part of the same project. When you tell Foundation which is your top level
entity, it will find all the sub-entities as long as they are in files
included in the same project. You don't need to mess around with
library definitions and so on.

Hope this helps.

If it doesn't, feel free to email me the code, and I'll give it a look-see.

-Kent.

[Andy Peters n o a o [.] e d u>]

I'll bet a six-pack of Bass Ale that you're not putting component
declarations in your code. For instance, in your top level, say you
have lower-level modules foo and bar. VHDL lets you do the following
direct instantiation:

architecture toplevel of mychip is
begin
u1 : entity work.foo
port map (...);
u2 : entity work.bar
port map (...);

However, FPGA Express is brain-dead and requires you to declare the
components before you instantiate them:

architecture toplevel_fpgaexpress of mychip is
component foo is
port (...);
end component foo;

component bar is
port (...);
end component bar;
begin
u1 : foo
port map (...);
u2 : bar
port map (...);

hope this helps.
-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool,
than to send an e-mail to the entire company
and remove all doubt."