I am passing in a signal to a component. The signal is not used
but I want to keep it there to have uniformity with other very similar
components. Synthesis gives me a warning, which I would like to
remove.
Do you know of any way that I can remove the warning while still
keeping the input port ?
Thanks
Bob
Hi Bob,
just attach a dummy signal to these ports.
I usually have two signals "high" and "low" that always keep a
'1' or a '0' for such purposes.
Btw., I don't know your design in detail, but leaving inputs
open might cause errors in the later stages of synthesis.
Regards,
Mario
Thanks for replying.
I am passing a signal "aft" which is a "000" into a component.
Now I don't use it in the component, but I pwant to keep it in
the port map. Synthesis tells me the signal is not used, but I
would like to avoid getting this synthesis warning while still
keeping the signal in the port map....If I set it to something in the
component, it'll give another warning...any ideas. ?
ste...@yahoo.com (Bob) wrote in message news:<20540d3a.03072...@posting.google.com>...
> I am passing a signal "aft" which is a "000" into a component.
> Now I don't use it in the component, but I pwant to keep it in
> the port map. Synthesis tells me the signal is not used, but I
> would like to avoid getting this synthesis warning while still
> keeping the signal in the port map....If I set it to something in the
> component, it'll give another warning...any ideas. ?
Ahhh, that's the issue - sorry.
But this warning is something you have to deal with. It is
a "friendly" remainder of your synthesis tool just to let you
know that these ports are not used, actually.
The only way to get rid of these warnings would be some
option of the synthesis tool like "-dont_warn_for_unused_ports".
But I doubt that there is such an option (check your user's manual).
Perhaps there is some option to skip all warnigns, but that's
perhaps not what you want.
What about piping stdout through some standard tools like grep
and remove these warnings in that way?
Regards,
Mario
You can try this: you define a dummy output port, let us call it oaft_dummy
in your example. Then you add within the entity's architecture code the
following statement:
oaft_dummy <= aft;
This statement is inserting net(s) from the input port aft to the output
port oaft_dummy, that is is directly connecting the output "pin(s)" of
the component to the input "pin(s)" of the component.
Finally, when instantiating the component you leave the dummy output port
open by mapping the ports as follows:
Inst: component_name port map ( ...
...
oaft_dummy => open,
...
... )
Regards,
Dan R