Does VHDL have an escape character ?

[Simon Kinahan]

Is there any way to escape illegal characters in identifiers in VHDL, the
way Verilog uses backslash ? I have a copy of the 1985 standard, and it doesn't
mention such a thing, but it seems like a major omission, so I was wondering
if one has been added since then.

Simon

[paul b. graham]

There is no 1985 standard. There was a 1987 standard, and there is now a
1993 standard. The 1993 standard defines a class of identifiers, called
extended identifiers, which may contain 'illegal' characters. Better even
than Verilog -- a VHDL extended identifier may contain a space. A VHDL
extended identifier is enclosed in '\' characters. For instance:

variable \#$)!?\ : integer;
variable \try this in verilog\ : bit;

Paul

[Bert Molenkamp]

Simon Kinahan <sim...@cadence.com> writes:
> Is there any way to escape illegal characters in identifiers in VHDL, the
> way Verilog uses backslash ? I have a copy of the 1985 standard, and it doesn't
> mention such a thing, but it seems like a major omission, so I was wondering
> if one has been added since then.
>

Yes.

In the LRM you refer to (probably the VHDL Std. 1076-1987, or a DoD document) there
was not a way to use "extended" identifiers.

But in the VHDL standard Std. 1076-1993 (page 174) you can use extended identifiers using a
... backslash at the beginning AND at the end.

\So this is one identifier\

It is level sensitive too. So \BUS\ is different from \bus\.

Egbert Molenkamp
Dept. of Computer Science
University of Twente
PO Box 217
7500 AE Enschede
the Netherlands
email: mole...@cs.utwente.nl