signed numbers in VHDL

[Tony Nelson]

Hello,

I want to use signed numbers in VHDL. for example,

m0 <=
std_logic_vector(signed(w11)*signed(conv_std_logic_vector(k(0),vwidth+1)));

i want to multiply the vector w11 (which will always be positive) by the
integer k, which will sometimes be negative. I want my output vector m0 to
be signed, so that the most significant bit displays the sign of the vector.
If I understand correctly, the above statement will be fine for that purpose
(correct me if I'm wrong). but if I take m0 and add it to another signed
vector, how do I do this?

It seems to me that I would need to take all bits except for the sign bit
and add them together. But this won't pick up the possible negative value
of the vector. Or does a statement like

a10 <=std_logic_vector(signed(m0)+signed(m1))

take into account the signed nature and add based on the sign?

What I'm trying to ask here is how to do mathematical operations using
signed data. if anyone has some good tips, please post them.

Thanks
Tony

[Srinivasan Venkataramanan]

Hi,
I have just now found a decent way of working with Signed
numbers. Hopefully this should be of some use to you.

Please see below:

> Hello,
> I want to use signed numbers in VHDL. for example,

> m0 <= std_logic_vector(signed(w11)*signed(conv_std_logic_vector
(k(0),vwidth+1)));

> i want to multiply the vector w11 (which will always be
positive) by the
> integer k, which will sometimes be negative. I want my output
vector m0 to
> be signed, so that the most significant bit displays the sign
of the
> vector. If I understand correctly, the above statement will be
fine for
> that purpose (correct me if I'm wrong). but if I take m0 and
add it to
> another signed vector, how do I do this?

If you want "m0" to be a signed number, then why do you do
an "explicit type conversion to a std_logic_vector"? I prefer
using "SIGNED" and "UNSIGNED" for arithmetic computations rather
than "std_logic_vector".

See a simple example below:
I choose your w11 to be a 4 bit vector and say it
as "UNSIGNED". I declare "m0_si" as 1 bit more in length than
a normal, unsigned multiplication (which in this case would
return a 8 bit vector - as far as I understand).

Signal m0_si : SIGNED (8 downto 0);
signal w11_us : unsigned (3 downto 0);
signal k_int : integer;

m0_si <= signed ( '0' & w11_us ) * to_signed(k_int,5);

-- to perform a signed *, I convert your w11_us to a "SIGNED
-- Positive" no. by concatenating with '0'.

-- I use "to_signed" conversion function from numeric_std. I
-- would recommend you NOT to use functions
-- like "conv_std_logic" etc. - they are NOT Standard ones.

I haven't checked this code, but I believe this should atleast
serve as a base for you to develop.

> but if I take m0 and add it to another signed
>vector, how do I do this?
>
>It seems to me that I would need to take all bits except for
the sign bit
>and add them together. But this won't pick up the possible
negative value
>of the vector. Or does a statement like
>
>a10 <=std_logic_vector(signed(m0)+signed(m1))
>
>take into account the signed nature and add based on the sign?
>

I guess a modified version of this should do - again this is
just a guess. You have to verify it yourself.

Again, I would declare the result "a10" as a SIGNED vector. and
do this

a10_si <= m0_si + m1_si;

-- Since as you said both m0 & m1 are signed, I don't see a need
for an explicit type conversion.

Regards,
Srini

>What I'm trying to ask here is how to do mathematical
operations using
>signed data. if anyone has some good tips, please post them.
>
>Thanks
>Tony
>
>
>
>

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[Berni Joss]

> integer k, which will sometimes be negative. I want my output vector m0
to
> be signed, so that the most significant bit displays the sign of the
vector.

I am not sure I understood you correctly, but it seems to me that the
representation of signed numbers you are expecting differs from the one used
in e.g. std_logic_arith package.
For example a value of -5 could be assigned as follows:
signal m0 : signed(7 downto 0);
m0 <= "11111011";

where as the following:
m0 <= "10000101";
would assign the value of -123, and not -5 as you might have expected.

The signed numbers are represented in 2's complement.

> If I understand correctly, the above statement will be fine for that
purpose
> (correct me if I'm wrong). but if I take m0 and add it to another signed
> vector, how do I do this?

Addition of 2's complement numbers is done exactly the same way as "normal"
binary numbers.

> It seems to me that I would need to take all bits except for the sign bit
> and add them together. But this won't pick up the possible negative value
> of the vector. Or does a statement like
>
> a10 <=std_logic_vector(signed(m0)+signed(m1))

This should actually work, if a10 is a std_logic_vector. But much easier you
can write:

signal a10, m0, m1 : signed(7 downto 0);
a10 <= m0 + m1;

Note that overflow conditions need to be handled explicetly by your code.
For example:

signal a10 : signed(8 downto 0);
signal m0, m1 : signed(7 downto 0);
a10 <= (m0(7)&m0) + m1;

the "+" operator for signed arguments automatically sign-extends the shorter
of the two arguments before performing the addition. a10(8) now contains the
carry/borrow bit.

I don't have access to the numeric_std package, but expect it to be
compatible with std_logic_arith, at least on this point.

Hope this helps,
Berni.

[jeff]

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

k and w are std_logic_vector(11 downto 0)
m0 is std_logic_vector(12 downto 0)

w is always positive
k may be negative

m0<= unsigned('0'&w) + unsigned (k(11)&k);

it works and the sign-extends is explicit...

[Srinivasan Venkataramanan]

Hi Jeff,
Well this has been discussed so many times before on this
NG, still just to re-emphasise my point of "avoid using
std_logic_arith" - For instance I can't simulate this code but I
can synthesise! Why? B'cos I use Cadence for Simulation and
Synopsys for Synthesis. The "std_logic_arith" from Cadence
doesn't define this "UNSIGNED" data type at all, whereas the one
from Synopsys does!

Hope you appreciate my view. I would rather use "numeric_std", as
much as possible (for me it is always possible)

Kind Regards,
Srini

In article <87roc0$7u4$1...@jaydee.iway.fr>, "jeff"

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[jeff]

Srinivasan Venkataramanan a écrit dans le message
<05ad2dd0...@usw-ex0101-006.remarq.com>...

>Hi Jeff,
> Well this has been discussed so many times before on this
>NG, still just to re-emphasise my point of "avoid using
>std_logic_arith" - For instance I can't simulate this code but I
>can synthesise! Why? B'cos I use Cadence for Simulation and
>Synopsys for Synthesis. The "std_logic_arith" from Cadence
>doesn't define this "UNSIGNED" data type at all, whereas the one
>from Synopsys does!
>
>Hope you appreciate my view. I would rather use "numeric_std", as
>much as possible (for me it is always possible)

You true, your view is usefull and interesting.

Best Regards,

Jeff