synthesis an implicit state machine
Udo Krebelder
is it possible to synthesize the following code with synopsis tools?
Menthor's Leonardo can not deal with it...
Udo
--
entity muller is
port(
a, b: in bit;
q: out bit
);
end muller;
architecture behavior of muller is
begin
process
begin
wait until a = '1' and b = '1';
q <= '1';
wait until a = '0' and b = '0';
q <= '0';
end process;
end behavior;
me...@mench.com
<u.kre...@kreuzgruber.com> wrote in article
<38206EFF...@kreuzgruber.com>:
> is it possible to synthesize the following code with synopsis tools?
I suspect not, but I'm just guessing....
> Menthor's Leonardo can not deal with it...
I'm not surprised. Exact adherence required multiple-clock
sensitivity, which is not a feature of any synthesis tools of which
I'm aware.
> entity muller is
> port(
> a, b: in bit;
> q: out bit
> );
> end muller;
> architecture behavior of muller is
> begin
> process
> begin
> wait until a = '1' and b = '1';
> q <= '1';
> wait until a = '0' and b = '0';
> q <= '0';
> end process;
> end behavior;
Perhaps if you changed the process to:
process
begin
wait on Clk until clk = '1' and a = '1' and b = '1';
q <= '1';
wait on Clk until clk = '1' and a = '0' and b = '0';
q <= '0';
end process;
(Of course, now you'll need a Clk input.) Now, the process is
sensitive to only a single clock. Of course, the wait statements are
now also rather complex, so the tools may still not understand....
Paul
--
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Thomas Hellerforth
Hi Udo,
try this:
architecture behavior of muller is
begin
process(a,b)
begin
if (a = '1' and b = '1') then
q <= '1';
end if;
if (a = '0' and b = '0') then
q <= '0';
end if;
end process;
end behavior;
bye
--
Thomas
________________________________________
Thomas Hellerforth
(Thomas.He...@post.rwth-aachen.de)
Marienbongard 10
52062 Aachen
jain_...@my-deja.com
you can always use code like this
fsm:process(a,b)
begin
if (a = '1' and b ='1') then
q <= '1';
elsif (a = '0' and b ='0') then
q <= '0'
end if;
end process;
but if you are really designing, you will never write such a
code these days. you don't have any clock in the design and
hence the combinational loops ie. inferring latches.
the best way is, you can use a clock
fsm:process
begin
wait unitl CLK ='1' and CLK'event;
if (a = '1' and b ='1') then
q <= '1';
elsif (a = '0' and b ='0') then
q <= '0'
end if;
end process;
this logic will be o.k. but you will say, this is not what I want.
Well! then we should not synthesize a pure behavorial code that
tools don't support right now.
In article <38206EFF...@kreuzgruber.com>,
Udo Krebelder <u.kre...@kreuzgruber.com> wrote:
> Dear All,
>
> is it possible to synthesize the following code with synopsis tools?
> Menthor's Leonardo can not deal with it...
>
> Udo
>
> --
> entity muller is
> port(
> a, b: in bit;
> q: out bit
> );
> end muller;
>
> architecture behavior of muller is
> begin
> process
> begin
> wait until a = '1' and b = '1';
> q <= '1';
> wait until a = '0' and b = '0';
> q <= '0';
> end process;
> end behavior;
>
Sent via Deja.com http://www.deja.com/
Before you buy.
Berni Joss
Is the following concurrent assignment equivalent to Udo's original process?
architecture behavior of muller is
begin
q <= a when a=b;
end behavior;
Berni.
Udo Krebelder <u.kre...@kreuzgruber.com> wrote in message
news:38206EFF...@kreuzgruber.com...
jain_...@my-deja.com
it is not equivalent to the Udo's original process?
a and b may be std_logic_vectors. so for x' and u's,
q would be x or u. but for undefined combinations,
we want to keep the old value of q.
naveen
me...@mench.com
wrote in article <94165840...@unet.urbanet.ch>:
> I'm quite new to vhdl ... Is the following concurrent assignment
> equivalent to Udo's original process?
> architecture behavior of muller is
> begin
> q <= a when a=b;
> end behavior;
Your concurrent assignment is equivalent to the following process:
process
begin
if a=b then
q <= a;
end if;
wait on a, b;
end process;
So, I believe it is.
> Udo Krebelder <u.kre...@kreuzgruber.com> wrote in message
> news:38206EFF...@kreuzgruber.com...
>> Dear All,
>>
>> is it possible to synthesize the following code with synopsis tools?
>> Menthor's Leonardo can not deal with it...
>>
>> Udo
>>
>> --
>> entity muller is
>> port(
>> a, b: in bit;
>> q: out bit
>> );
>> end muller;
>>
>> architecture behavior of muller is
>> begin
>> process
>> begin
>> wait until a = '1' and b = '1';
>> q <= '1';
>> wait until a = '0' and b = '0';
>> q <= '0';
>> end process;
>> end behavior;
Paul
vhdl
>
> Dear All,
>
> is it possible to synthesize the following code with synopsis tools?
> Menthor's Leonardo can not deal with it...
>
> Udo
>
> --
> entity muller is
> port(
> a, b: in bit;
> q: out bit
> );
> end muller;
>
> architecture behavior of muller is
> begin
> process
> begin
> wait until a = '1' and b = '1';
> q <= '1';
> wait until a = '0' and b = '0';
> q <= '0';
> end process;
> end behavior;
Hello Udo,
perhaps it would be synthesizable if you have a technology
library containing a muller C element.
For "normal" libraries i think it is not possible.
(most of the VHDL world thinks 'synchronous' as you can see
in the answers posted here in the newsgroup ...)
A workaround would be to build the muller C element out of basic
gates. Nevertheless you will have problems as there are some timing
constraints to be met for correct function.
The code could be like:
I1 <= A and B ;
I2 <= A or B ;
I3 <= I2 and QI ;
QI <= I1 or I3 ;
Q <= QI ;
Viel Spass,
Martin Padeffke
--
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me...@mench.com
article <7vqfu3$kou$1...@nnrp1.deja.com>:
> it is not equivalent to the Udo's original process?
> a and b may be std_logic_vectors. so for x' and u's,
Nope, look at the original. Both are declared as bits.
> q would be x or u. but for undefined combinations,
> we want to keep the old value of q.
> naveen
> "Berni Joss" <berni...@urbanet.ch> wrote:
>> I'm quite new to vhdl ...
>> Is the following concurrent assignment equivalent to Udo's original
> process?
>>
>> architecture behavior of muller is
>> begin
>> q <= a when a=b;
>> end behavior;
>>
>> Berni.
>>
>> Udo Krebelder <u.kre...@kreuzgruber.com> wrote in message
>> news:38206EFF...@kreuzgruber.com...
>> > Dear All,
>> >
>> > is it possible to synthesize the following code with synopsis tools?
>> > Menthor's Leonardo can not deal with it...
>> >
>> > Udo
>> >
>> > --
>> > entity muller is
>> > port(
>> > a, b: in bit;
>> > q: out bit
>> > );
>> > end muller;
>> >
>> > architecture behavior of muller is
>> > begin
>> > process
>> > begin
>> > wait until a = '1' and b = '1';
>> > q <= '1';
>> > wait until a = '0' and b = '0';
>> > q <= '0';
>> > end process;
>> > end behavior;
>>
>>
> Sent via Deja.com http://www.deja.com/
> Before you buy.