Write Output Signal in Text File

[Basuki Endah Priyanto]

Dear all,

The output signal of my design is so called "data_out". So far this output can be viewed from my computer screen. The problem is when I try to write this output into a text file.

For example, I tried to write the following command in my test-bench:

ENTITY testfilrx_tester IS
PORT(
data_out : IN std_logic_VECTOR (11 DOWNTO 0);
RDY_RX : IN std_logic;
CLK4f : OUT std_logic;
IN_IF : OUT std_logic_VECTOR (11 DOWNTO 0);
RESET : OUT std_logic;
START : OUT std_logic
);

----deleted------

writing_stage : process(RDY_RX)
file outfile: TEXT IS OUT "c:\project\output.txt";
variable L1: LINE;
Variable temp : std_logic_vector (11 downto 0);
Begin
if (RDY_RX='1' and RDY_RX'event) then
tampa :=data_out;
write(l1,temp);
writeline(outfile,l1);
end if;
end process;

However, I've got error message when I compiled it :
ERROR: C:/Project/digimod/hdl/testfilrx_tester_testfilrx_tester_behav.vhd(75): No feasible entries for subprogram write

Anyone can help me ?

Really appreciate that !

Thanks

Buzz

[Andre Powell]

Hi Basuki,
Write can only accept bit, bit_vector, unsigned and char, what you need to
do is create a new function
will take the std_logic/std_logic. The way that I have done it is by
creating a function and then traversing the
vector and converting the indiviual bits to equivalent chars and then
sending the string out. Remember you need to
write an equivalent read function.

Best Regards

Andre'
"Basuki Endah Priyanto" <EBEPr...@ntu.edu.sg> wrote in message
news:tEUUUua2...@exchnews1.main.ntu.edu.sg...

[VhdlCohen]

Use the image package from my site, under models&papers
---------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdl...@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

[RBD]

Hello,

I Read the links below and had a question. I am trying to read REAL
type samples and write REAL type files in VHDL. Reading the link below
it seems that if write is only type bit,bit_vector,unsigned, and char
then is read also the same? So how do you read in a file of REAL TYPE?
Does one have to do some external manipulation like with a small Perl
program or something? It would seem there should be a way in VHDL to
read and write real values.

Thanks for any info.

RBD

vhdl...@aol.com (VhdlCohen) wrote in message news:<20030221115258...@mb-fr.aol.com>...

[Basuki Endah Priyanto]

Hi All,

My problem is solved after I add the following package:

use IEEE.std_logic_textio.all;

Thanks :)

Rgds,

Buzz

[Srinivasan Venkataramanan]

Hi,

"Andre Powell" <andre....@ntlworld.com> wrote in message
news:mWp5a.198$Va2.60477@newsfep2-gui...

> Hi Basuki,
> Write can only accept bit, bit_vector, unsigned and char, what you need to
> do is create a new function
> will take the std_logic/std_logic.

Synopsys had created such a set of functions and is generally available
under ieee.std_logic_textio package (though it is not official IEEE due to
its wide spread usage all major vndors tend to provide this).

> Anyone can help me ?
>

Add the following two lines at the top of your file.

library ieee;
use ieee.std_logic_textio.all;

> Really appreciate that !
>
> Thanks
>
> Buzz
>
>

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

I don't speak for Intel
Visit: http://www.noveldv.com

[RBD]

Hi,

I am trying to read a file of real type and get the following error
below:

ERROR: ../vhdl_src/fir_tb.vhd(127): No feasible entries for
subprogram read

I got this even after adding the textio package. I am running modelsim
5.6e.

Any help appreciated.

-RBD

snippet of code:
**********************************************************************

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use work.config.all;

read_matlab_samples : process --is

subtype real_entries is real;
type load_file_type is file of real_entries;
file load_matlab_file : load_file_type open read_mode is
"matlab_input_samples";

subtype natural is integer range 0 to 66; -- later parameterize this
similar to verilog construct

type sample_array is array( natural range 0 to 66) of real_entries;
--variable matlab_sample : real;
variable matlab_sample : sample_array;
variable sample_length : natural;

begin
while not endfile( load_matlab_file) loop
read(load_matlab_file, matlab_sample);--, sample_length);
--if sample_length > sample`length then
--report " matlab has too many samples--ignored" severity
warning;
--else
for sample_index in 1 to sample_length loop
wait until CLK = '1';
INPUT_FOR_FIR <= not INPUT_FOR_FIR;
wait until CLK = '0';
INPUT_FOR_FIR <= INPUT_FOR_FIR xor
matlab_sample(sample_index);
end loop;
--end if;
end loop;
wait;
end process read_matlab_samples;
********************************************************************************

"Basuki Endah Priyanto" <EBEPr...@ntu.edu.sg> wrote in message news:<twBKR0h2...@exchnews1.main.ntu.edu.sg>...

> Hi All,
>
> My problem is solved after I add the following package:
>

> use IEEE.std logic textio.all;

>
> Thanks :)
>
> Rgds,
>
> Buzz
>
> > -----Original Message-----
> > From: Basuki Endah Priyanto
> > Sent: Friday, February 21, 2003 9:17 PM
> > Posted To: vhdl
> > Conversation: Write Output Signal in Text File
> > Subject: Write Output Signal in Text File
> >
> > Dear all,
> >

> > The output signal of my design is so called "data out". So far this

> output can be viewed from my computer screen. The problem is when I try
> to write this output into a text file.
> >
> > For example, I tried to write the following command in my test-bench:
> >

> > ENTITY testfilrx tester IS
> > PORT(
> > data out : IN std logic VECTOR (11 DOWNTO 0);
> > RDY RX : IN std logic;
> > CLK4f : OUT std logic;
> > IN IF : OUT std logic VECTOR (11 DOWNTO 0);
> > RESET : OUT std logic;
> > START : OUT std logic
> > );
> >
> > ----deleted------
> >
> > writing stage : process(RDY RX)

> > file outfile: TEXT IS OUT "c:\project\output.txt";
> > variable L1: LINE;

> > Variable temp : std logic vector (11 downto 0);
> > Begin
> > if (RDY RX='1' and RDY RX'event) then
> > tampa :=data out;

> > write(l1,temp);
> > writeline(outfile,l1);
> > end if;
> > end process;
> >
> > However, I've got error message when I compiled it :
> > ERROR:

> C:/Project/digimod/hdl/testfilrx tester testfilrx tester behav.vhd(75):

[Srinivasan Venkataramanan]

Hi,
READ is overloaded to work with REAL data type by std.textio package by
default. The problem I think you are facing is due to the fact that you are
trying to define your own file type etc. Use predefined TEXT type.

Here is a simple VHDL (and a sample data.txt) to read real from a file.

HTH,
Srinivasan

---- read_real.vhdl -------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity test is
end entity test;
architecture a of test is
begin
read_p : process
file data_file : text open read_mode is "data.txt";
variable L : line;
variable tmp_real : real;
variable line_no : integer := 0;
variable flag : boolean;
variable res_str : string (1 to 9) := " FAILURE ";
begin
while not endfile (data_file) loop
line_no := line_no + 1;
readline(data_file, L);
read(L => L, value => tmp_real, good => flag);

if (flag) then
res_str := " SUCCESS ";
report " Value read is " & real'image(tmp_real);
else
res_str := " FAILURE ";
end if;

report " Read from line no. " & integer'image(line_no) &
" was a " & res_str;
end loop;
WAIT;
end process read_p;

end architecture a;

--- a sample data.txt with a ILLEGAL value as well! ---

10.25
a1
1.0

"RBD" <baycoo...@yahoo.com> wrote in message
news:9f7f3827.03022...@posting.google.com...

> Hi,
>
> I am trying to read a file of real type and get the following error
> below:
>
> > >

--

Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

I don't speak for Intel

http://www.noveldv.com

[Basuki Endah Priyanto]

Hi,

From the error message, it seems like you miss out package declaration. you need to define floating point package declaration as you are using real operation.

Please read the following URL :

http://www.eda.org/fphdl/hm/0011.html

Regards,

Basuki Keren Abizz

-----Original Message-----
From: RBD [mailto:baycoo...@yahoo.com]
Posted At: Wednesday, February 26, 2003 9:01 AM
Posted To: vhdl
Conversation: Write Output Signal in Text File

Subject: Re: Write Output Signal in Text File

Hi,

I am trying to read a file of real type and get the following error
below:

ERROR: ../vhdl_src/fir_tb.vhd(127): No feasible entries for