I want to learn to do a testbench for my FIR filter.

[Daniel Yap]

Hello,

I have designed a 8-Bits, 16 Taps FIR filter. Now, the problem is I am very
keen to learn how to display my answer correctly. I ask some friends, and
they told me that I can do a testbench for it. So, I am asking for something
help and guideline about where I can find some resources about doing it. For
information, I designed my filter with VHDL.

Thank you.

Daniel

[Ray Andraka]

A testbench is just another VHDL program in which you instantiate your design.
In the testbench you write VHDL to generate the stimulus (and often check the
outputs) of the design under test. Since testbenches are for simulation only,
you can use the parts of VHDL that are not usable for synthesis. Examples are
the math_real library of functions, wait delays (wait for x ns or wait until
signal). A simple test bench might just supply clock and generate an impulse
for your DUT. A more complicated one can read a waveform from a file and store
the output in another file.

Daniel Yap wrote:

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email r...@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

[VhdlCohen]

A testbench 9TB) style that has gained popularity is the transaction based TB
model. The testbench includes
1. transactor(s) (or client) , a model that asserts transactions to be
executed, such as READ, WRITE, FAULT, DMA, INTERRUPT

2. transaction execution models (server), that gets the instruction from the
client, and provides the low level interface to the UUT, unit under test.

3. Verifier, to verify UUT. Verifier reads the client requested transactions,
and the UUT ouputs (or internal nodes) to determine if UUT is performing
correctly. As Ray said, the models can use other packages (e.g., math) and
files in the definition and verification of the UUT.

This type of style is demonstrated in VHDL and Verilog in my "Real Chip Design
and Verification" book, and in VHDL with files and a reusable parser in
"Component Design by Example" book.
Ben
---------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdl...@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

From: Ray Andraka r...@andraka.com
Date: 1/25/02 11:32 AM Pacific Standard Time
Message-id: <3C51B3FA...@andraka.com>

A testbench is just another VHDL program in which you instantiate your design.
In the testbench you write VHDL to generate the stimulus (and often check the
outputs) of the design under test. Since testbenches are for simulation only,
you can use the parts of VHDL that are not usable for synthesis. Examples are
the math_real library of functions, wait delays (wait for x ns or wait until
signal). A simple test bench might just supply clock and generate an impulse
for your DUT. A more complicated one can read a waveform from a file and store
the output in another file.

[Srinivasan Venkataramanan]

Hi Daniel,
You may want to start looking at:
http://i2.i-2000.com/~stefan/vcourse/html/

Good Luck,
Srinivasan

"Daniel Yap" <dani...@hotmail.com> wrote in message
news:3c51a...@news.tm.net.my...

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India, Visit: http://www.simputer.org)
"I don't Speak for Intel"