Timing Analysis CAD Tool

[d2fab...@aol.com]

Hello All

I've been working on a program called the TimingAnalyzer. I started this
effort cause I didn't want to pay the high prices for the programs like
this one, and I could add features as needed.

Current features:

1) draw timing diagrams in graphical interface.
2) cut and paste diagrams in word processing documents
3) do static timing analysis (min, typ, and worst case)
4) edit/add to parts libraries in text files
5) edit/add to signal diagrams in text files
6) generate test vectors for logic simulators.
7) generate input stimulus pwl formatted vectors for spice.
8) cross platform application written in Java.

Feature that will be added:

1) dynamic timing analysis (min:typ typ:max min:max margins )
2) logic simulation
3) schematic integration

You can see the TimingAnalyzer at

http://members.aol.com/d2fabrizio

Iam considering the following:

1) making it shareware
2) including it in a Digital System Design text book
3) allow others to add to the effort by going open source

I would appreciate any ideas, suggestions, or comments.

Please email me at

d2fab...@aol.com

Thanks,
Dan Fabrizio

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own

[Bruce Nepple]

I wish I could get a good timing diagram editor. If you just do that, you
will have a product you can sell. If you do that part poorly, the other
features are useless (well, maybe not useless, but less useful).

Features for timing diagram tool

1. Add clocks quickly without building each edge
2. Curved Arrows to show cause and effect between waveforms
3. "Don't care" graphic (easily show area where input is "don't care)
4. Easily grab transitions and move them
5. Cut and paste
6. Move waveforms (change their order on the page) without losing reference
points
7. Easily show min/max edges with graphics in-between that makes it obvious
8. Timing reference lines can run under or over waveforms/text
9. Timing reference lines can run full page vertically
10. Notes and timing values can be annotated anywhere on the page
11. On tristate lines, you can have hash marks to show when the bus is not
valid

I could probably think of a few more if you are interested.
Email me if you want a tester. Remove .extra to send email

Bruce

d2fab...@aol.com wrote in message <76df9d$pn6$1...@nnrp1.dejanews.com>...

[David Pashley]

In article <mNvi2.1319$Q81....@news7.ispnews.com>, Bruce Nepple
<bru...@imagenation.extra.com> writes

>I wish I could get a good timing diagram editor. If you just do that, you
>will have a product you can sell. If you do that part poorly, the other
>features are useless (well, maybe not useless, but less useful).
>
>Features for timing diagram tool
>

<snip>

The market leading TD editor is TimingDesigner from Chronology (over
100,000 users). You can download a free limited evaluation copy from
www.chronology.com

Chronology also makes a product called QuickBench which uses timing
diagrams to generate testbench bus-functional models (VHDL/Verilog) from
interface specifications.

--
David Pashley <
--------------------------- < < < --- mailto:da...@edasource.com
| Direct Insight Ltd < < < < > Tel: +44 1280 700262 |
| http://www.edasource.com < < < Fax: +44 1280 700577 |
------------------------------ < ---------------------------------

[d2fab...@aol.com]

Hi David

I have used Chronology Timing Designer. It is a good tool, but
very expensive and very very expensive for large number of users or
multiple machines/platformes. The free demos are useless for real projects.

The TimingAnalyzer gives you the necessary functions needed for
drawing timing diagrams and doing static timing analysis. It is
very user friendly and someday will be available for a low cost or
shareware, or I might open the source code?

Iam also working on a web browser version, so anyone
with netscape or internet explorer can draw,edit, and analyze
timing diagrams.

Dan Fabrizio

In article <KN6wbYAR...@fpga.demon.co.uk>,

-----------== Posted via Deja News, The Discussion Network ==----------

[Brian Boorman]

That sounds like a commercial! Judging from your e-mail address I assume you
sell EDA products. If that is the case, it is generally proper etiquette to
identify your position as biased source.

David Pashley wrote:
<...snip...>

> The market leading TD editor is TimingDesigner from Chronology (over
> 100,000 users). You can download a free limited evaluation copy from
> www.chronology.com
>
> Chronology also makes a product called QuickBench which uses timing
> diagrams to generate testbench bus-functional models (VHDL/Verilog) from
> interface specifications.
>
> --
> David Pashley <
> --------------------------- < < < --- mailto:da...@edasource.com
> | Direct Insight Ltd < < < < > Tel: +44 1280 700262 |
> | http://www.edasource.com < < < Fax: +44 1280 700577 |
> ------------------------------ < ---------------------------------

--
Brian C. Boorman
Harris RF Communications
Rochester, NY 14610
XYZ.bb...@harris.com
<Remove the XYZ. for valid address>

[David Pashley]

In article <369B8A42...@harris.com>, Brian Boorman
<XZY.bb...@harris.com> writes

>That sounds like a commercial! Judging from your e-mail address I assume you
>sell EDA products. If that is the case, it is generally proper etiquette to
>identify your position as biased source.

No, it's not a commercial. It's an observation of fact which is relevant
to the subject of the thread and contains no opinions, and so can hardly
be biased.

Yes, Direct Insight is a UK-based reseller of EDA tools, including
Chronology's. I had assumed that this might be inferred from the domain
name, but if not, please accept my apologies.

>
>David Pashley wrote:
><...snip...>

[Dan Notestein]

SynaptiCAD's WaveFormer product offers more timing diagram editing
features, waveform import from simulators, and stimulus generation
capabilities for significantly less than TimingDesigner's cost. A free
evaluation can be downloaded from http://www.syncad.com.

Dan Notestein
SynaptiCAD inc

In article <KN6wbYAR...@fpga.demon.co.uk>, David Pashley
<Da...@edasource.com> wrote:
>In article <mNvi2.1319$Q81....@news7.ispnews.com>, Bruce Nepple
><bru...@imagenation.extra.com> writes
>>I wish I could get a good timing diagram editor. If you just do that, you
>>will have a product you can sell. If you do that part poorly, the other
>>features are useless (well, maybe not useless, but less useful).
>>
>>Features for timing diagram tool
>>
><snip>
>

>The market leading TD editor is TimingDesigner from Chronology (over
>100,000 users). You can download a free limited evaluation copy from
>www.chronology.com
>
>Chronology also makes a product called QuickBench which uses timing
>diagrams to generate testbench bus-functional models (VHDL/Verilog) from
>interface specifications.
>

For a FREE evaluation of Timing Diagrammer, WaveFormer, VeriLogger, or
TestBencher Pro, visit our web site: http://www.syncad.com
******************************************************************
SynaptiCAD, Inc. Sales: (800) 804-7073
P.O. Box 10608 Support: (540) 953-3390
Blacksburg, VA 24062-0608 Fax: (540) 953-3078
ftp: www.syncad.com email: sa...@syncad.com