Iteration limit error on ModelSim
Yongduck Seo
I got the message "Iteration limit reached. Possible zero
delay oscillation. See the manual." after simulation of
results of gate level synthesis by synopsis without any
sdf file. But that message did not come out when
I tried RTL level funtional simulation, of course, using
the same ModelSim. And I cannot find where that happen
in my code befer or after the systhesis.
What's the problem?
Does somebody have any idea?
Andy Peters
Why aren't you using the post-simulation SDF file? You may be getting
the races because you don't have the delays.
--a
Andrew Brown
think thats the default) and see if that helps.
It's unlikely you have a race which would generally mean a combinational
loop of some kind - this should produce a warning when synthesising (is the
netlist vhdl?).
A.
"Andy Peters" <an...@exponentmedia.deletethis.com> wrote in message
news:3BE2CAAC...@exponentmedia.deletethis.com...
Srinivasan Venkataramanan
You may want to try with +delay_mode_unit option, that may solve
the problem temporarily before you get your SDF.
Good Luck,
Srinivasan
--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India, Visit: http://www.simputer.org)
"Yongduck Seo" <yd...@pixelplus.co.kr> wrote in message
news:5829290d.01110...@posting.google.com...
Mike Treseler
>
> Hi,
>
> I got the message "Iteration limit reached. Possible zero
> delay oscillation"
Sounds like you've enabled an
asychronous oscillator.
Why not bring up the gui,
view source, trace the code
and see what's happening?
Might have to add a register or two.
--Mike Treseler
Narendran Kumaraguru Nathan
I seriously doubt a non-exit loop. Please check you code if any two
process trigger each other and keep on running
without incrementing of the simulation time. Please check if the
simulation time advances.
~Naren.