Set-Force with NC sim

[Anil Dalwani]

Hi all --

I want to force a value to some variables, but am not able to do so.

The vhdl code is like this :

entity declaration

architecture
signal declarations

begin
process

variable declarations
begin
a small code
wait
end process

end architecture

Now, I am able to force values on signals but not on variables. Could
anyone advise me why ? If I right click on variable names, then it
doesn't highlight the force assignment ( it does highlight the deposit
assignment) and if I do from menu , it says

"Cannot Force a VHDL variable. Use 'deposit' command to modify the
variable's value " . I suppose I should be able to force a value to
varialbe . Shouldn't I ?

Thanks in advance,

Anil.

[Srinivasan Venkataramanan]

Hi Anil,
As the Help says use "deposit" for VHDL Variables - wouldn't
that be sufficient for you? I can imagine situations where it won't be
:-) (if you can explain your situation better may be someone can help
you overcome that). But I *guess* they don't allow "force" on
Variables b'cos they (EDA vendors) *might* have probably thought that
Variables are "short lived" (as in some programming languages), may be
I am wrong, I am no EDA tool developer anyway.

Regards,
Srinivasan

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India, Visit: http://www.simputer.org)
"I don't Speak for Intel"

"Anil Dalwani" <adal...@binghamton.edu> wrote in message
news:c4ecc514.01112...@posting.google.com...

[Sule Cetin]

you can force the variable using the "deposit" command, lets say your
variable is

variable temp : std_logic;

then on your ncsim window:

ncsim> deposit temp = '1'

will force your variable(sould care about the type)

[Srinivasan Venkataramanan]

Hi,
The difference is that (AFAIK, didn't try and example) "force" will
keep the value the SAME (as forced) until a "release" (followed by an
assignment from elsewhere) or another "force" is applied while
"deposit" does it for just this "time step" and any other assignment
*may* override it straight away.

Srinivasan

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India, Visit: http://www.simputer.org)
"I don't Speak for Intel"

"Sule Cetin" <sule....@powervr.com> wrote in message
news:EA21125BE8B4D5119E7...@smtp1.videologic.co.uk...

> you can force the variable using the "deposit" command, lets say
your
> variable is
>
> variable temp : std_logic;
>
> then on your ncsim window:
>
> ncsim> deposit temp = '1'
>
>
> will force your variable(sould care about the type)
>

> <SNIP>