VHDL 2008: Can I use conditional_expressions as an initialiser for a constant?

[Allan Herriman]

Hi,

I'm trying to do something equivalent to the following:

generic g : boolean;

...

constant c : some_type := expression1 when g else expression2;


This is something I want to do a lot in both synthesisable and non-
synthesisable designs. Usually I end up writing an 8 line function to do
something that I ought be able to do in a single line.

For example, in Verilog 2001 I would write this as

localparam c = g ? expression1 : expression2;


(Questions below)

I found this in the '08 standard:

[§ 6.4.2.2]
constant_declaration ::=
constant identifier_list : subtype_indication [ := expression ] ;

[§ 9.1]
expression ::=
condition_operator primary
| logical_expression

[§ 9.1]
primary ::=
name
| literal
| aggregate
| function_call
| qualified_expression
| type_conversion
| allocator
| ( expression )

Unfortunately, "expression" doesn't ever lead to
"conditional_expressions".

[§ 10.5.3]
conditional_expressions ::=
expression when condition
{ else expression when condition }
[ else expression ]


Questions:

Q1: Am I reading the standard correctly and we can't (in 2008) use
conditional expressions in constant initialisers?

Q2: Is there some simple and effective way of doing what I'm trying to do?

Q3: If not, how do we go about fixing this?


Thanks,
Allan

[KJ]

On Wednesday, November 26, 2014 6:21:16 AM UTC-5, Allan Herriman wrote:
> Hi,
>
> I'm trying to do something equivalent to the following:
>
> generic g : boolean;
> ...
> constant c : some_type := expression1 when g else expression2;
>

<snip>

>
> Q3: If not, how do we go about fixing this?
>
>

Write a function that takes as input the condition and the two expressions and returns the result. I called mine 'sel' (since 'select' is already a reserved keyword). Overload it for all of the basic types that you would use for an expression as well as for std_ulogic and boolean for the condition. Works just fine for any version VHDL.

function sel(Cond: BOOLEAN; If_True, If_False: integer) return integer;
function sel(Cond: BOOLEAN; If_True, If_False: real) return real;
function sel(Cond: BOOLEAN; If_True, If_False: time) return time;
function sel(Cond: BOOLEAN; If_True, If_False: BOOLEAN) return BOOLEAN;
function sel(Cond: BOOLEAN; If_True, If_False: arr_integer) return arr_integer;
function sel(Cond: BOOLEAN; If_True, If_False: arr_natural) return arr_natural;
function sel(Cond: BOOLEAN; If_True, If_False: arr_real) return arr_real;
function sel(Cond: BOOLEAN; If_True, If_False: arr_time) return arr_time;
function sel(Cond: BOOLEAN; If_True, If_False: std_ulogic) return std_ulogic;
function sel(Cond: BOOLEAN; If_True, If_False: std_ulogic_vector) return std_ulogic_vector;
function sel(Cond: BOOLEAN; If_True, If_False: std_logic_vector) return std_logic_vector;
function sel(Cond: BOOLEAN; If_True, If_False: signed) return signed;
function sel(Cond: BOOLEAN; If_True, If_False: unsigned) return unsigned;
function sel(Cond: BOOLEAN; If_True, If_False: STRING) return STRING;
function sel(Cond: BOOLEAN; If_True, If_False: Character) return Character;

Then the usage is simply:

constant c : some_type := sel(g, expression1, expression2);

Or for the more wordy

constant c : some_type := sel(Cond => g, If_True => expression1, If_False => expression2);

Kevin Jennings

[Andy]

There is no such thing in vhdl as "conditional expressions", only "conditional assignments". Since your statement is not an assignment statement, but a declaration statement, your code is non-compliant.

Andy

[Jim Lewis]

Hi Allan,
I worked on it for the VHDL-2008 phase. It is an interesting problem as to how to add it as an expression given that signals assignments already have existing conditional_waveforms. Also one of the members wanted to change the else to a "," (in the name of conciseness) in the conditional assignment. In the end that caused ambiguity which killed it.

During the LRM editing phase, I got busy with other items (had to work so I could eat), and did not notice that the force statement required a separate BNF production that defined conditional_expression. Wish I had noticed as given that it was done there, it is very obvious to support that in at least an initialization scenario as you asked for.

It is on the list again:
http://www.eda.org/twiki/bin/view.cgi/P1076/ConditionalExpressions

I added a fail safe so that if the main proposal fails that we at least add it to initialize constants, signals, and variables. Which seems to be a trivial addition at this point.

We are at the point where we are ranking proposals and welcome input from members of the VHDL community - no one want to add and/or implement features that are not wanted by the general community.

Jim