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Array Initialization in VHDL-2008
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Digital Guy
Feb 17, 2022, 12:59:59 PM2/17/22
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The following array initialization worked fine in VHDL-2002:
type PACKET_REG_TYPE is array (0 to PACKET_LEN_MAX - 1) of std_logic_vector(7 downto 0); -- Packet array definition: (PACKET_LEN_MAX) deep x 8-bit wide.
signal tx_byte_sr : PACKET_REG_TYPE;
tx_byte_sr <= (others => (others => '0'));
Now, with VHDL-2008, it gives: (vcom-1320) Type of expression "(OTHERS => '0')" is ambiguous; using element type STD_LOGIC_VECTOR, not aggregate type PACKET_REG_TYPE.
I can't find any documentation on the "new" way to initialize arrays in VHDL-2008.
type PACKET_REG_TYPE is array (0 to PACKET_LEN_MAX - 1) of std_logic_vector(7 downto 0); -- Packet array definition: (PACKET_LEN_MAX) deep x 8-bit wide.
signal tx_byte_sr : PACKET_REG_TYPE;
tx_byte_sr <= (others => (others => '0'));
Now, with VHDL-2008, it gives: (vcom-1320) Type of expression "(OTHERS => '0')" is ambiguous; using element type STD_LOGIC_VECTOR, not aggregate type PACKET_REG_TYPE.
I can't find any documentation on the "new" way to initialize arrays in VHDL-2008.
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