ASRC (asynchronus sample rate conversion)

[Damir Danijel Zagar]

I'm in need of a pointer for a ASRC implementation
using DSP or FPGA. Any source (C-code or VHDL)
will be more than welcome. Regards,

Damir

[robert bristow-johnson]

In article <9stchu$kdl$1...@sunce.iskon.hr> , "Damir Danijel Zagar"
<dza...@srce.hr> wrote:

you ain't gonna get any C code from me (it belongs to the company), but i
did implement such a thing on the SHArC about 5 or 6 years ago.

Bob Adams of Analog Devices is essentially the father of the ASRC chip
(AD-1890 and relatives) and the only on-line publication i can find from him
about this is at:

http://www.analog.com/industry/audio/documents/92AES.pdf

there are two independent concepts to get down. the first is the basics of
"resampling" or "polyphase filtering" or "bandlimited interpolation" or
"sample rate conversion" (whether it's asynchronous or not) or whatever is
the jargon that's currently in vogue for it. a primer can be found at:

http://groups.google.com/groups?selm=387e71db.0%40news.viconet.com

the second concept to get down is the servo control mechanism to adjust the
sampling ratio between input and output that is based purely on the
asynchronous input and output word clocks. the Bob Adams paper to look that
up is not online (as best as i can tell) but is published:

Adams & Kwan, "Theory and VLSI Archetectures for Asynchronous Sample-Rate
Converters", JAES, vol. 41, p. 539 (Jul 1993) .

--

r b-j

Wave Mechanics, Inc.
45 Kilburn St.
Burlington VT 05401-4750

tel: 802/951-9700 ext. 207 http://www.wavemechanics.com/
fax: 802/951-9799 rob...@wavemechanics.com

--

[Muzaffer Kal]

You can use a phase generator and a fractional delay filter to do
asynchronus sample rate conversion. A phase generator is simply a
modulus counter which calculates the sampling point of the target
clock on the data. Using this phase, you can calculate the newly
sampled data by interpolation. For interpolation, a fractional delay
filter can be used as implemented by a farrow filter. With a farrow
filter, you can use any polynomial interpolator.

hope this help,

Muzaffer Kal

http://www.dspia.com
DSP algorithm implementations for FPGA systems

[Jon Harris]

The datasheet for the AD1896 is a good place to look too. Bob designed this
chip and the data sheet has a lot of the theory.
http://www.analog.com/pdf/AD1896_0.pdf

"robert bristow-johnson" <rob...@wavemechanics.com> wrote in message
news:9hxI7.7619$o16.3...@typhoon2.gnilink.net...

[Brad Evans]

Another place to look is here:
http://www-s.ti.com/sc/psheets/slws130/slws130.pdf

This is a datasheet of a Graychip (now TI) digital resampler chip
developed awhile back and has some discussion of the interpolation
filter employed (4,096 15-tap sets). Used mostly for baud-timing
schemes in QAM demodulators and for sample rate adjustment of data
between different systems.

Brad Evans
http://www.graychip.com