readmemb or readmemh in VHDL

[Tig...@my-dejanews.com]

Hello,

I'm new to VHDL and please forgive me if someone already asking this question.
Is there a way to initialize memory like Verilog using readmemb or readmemh in
VHDL? Can you post the code or point me to the FAQ that I can read. Any help
is greatly appreciated. Thanks.

Tigers

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[Wolfgang Ecker]

Tig...@my-dejanews.com wrote:

Hi Tigers,

there is no pre-defined function doing so. What you can do is to implement a
function, which reads from a file and return the value of the array. This could
look like as follows:

--------------------------------------------------------------------------------
type mem_elem_type is ... -- as you wish
type mem_type is array( natural range 0 to 1023 ) of mem_elem_type;

function init_mem( file_name : string ) return mem_type is
variable tmp : mem_elem_type;
...
begin
-- open and parse your file here.

return( tmp );
end init_mem;

-- ... Somwhere

variable mem: mem_type := init_mem( "your_file" );
---------------------------------------------------------------------------------

Hope this helps

Wolfgang

[Bert Molenkamp]

Tig...@my-dejanews.com writes:
> Hello,
>
> I'm new to VHDL and please forgive me if someone already asking this question.
> Is there a way to initialize memory like Verilog using readmemb or readmemh in
> VHDL? Can you post the code or point me to the FAQ that I can read. Any help
> is greatly appreciated. Thanks.
>
> Tigers

In VHDL it is not possible to initialize a memory with a command like
$readmemh("datafile",memory);

I add an example how you can read data from a file (that demonstrates how it
can be used in a test bench).
In this example I used VHDL standard form 1987 (In the 1983 File IO is changed
procedures are changed).

File data.inp:
1 0 50 ns
0 0 50 ns
0 1 100 ns
0 0 50 ns
1 0 70 ns
0 0 50 ns

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test_set IS
PORT (set, reset : OUT std_ulogic := '0');
END test_set;

USE std.textio.ALL;
ARCHITECTURE TestSet2 OF test_set IS
BEGIN
PROCESS
VARIABLE delay : time;
VARIABLE setvar, resetvar : bit;
VARIABLE inp_line : line;
FILE in_data : text IS "data.inp";
BEGIN
LOOP
EXIT WHEN endfile(in_data);
readline(in_data, inp_line);
read(inp_line,setvar);
read(inp_line,resetvar);
read(inp_line,delay);
set <= To_StdUlogic(setvar);
reset <= To_StdUlogic(resetvar);
WAIT FOR delay;
END LOOP;
WAIT;
END PROCESS;
END TestSet2;

Regrads,
Egbert Molenkamp