Multiple Drive Error

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Ceyhun Sarıkaya

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Mar 18, 2021, 12:45:43 PM3/18/21
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Hi
I am getting this error.
My block design is this (https://www.linkpicture.com/q/Screenshot-2021-03-18-150349.png)

I think needs to be added Mux in FIFO port map. How could I add MUX inside of this code?

Thank you so much
Regards

My scripts like that;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Library UNISIM;
use UNISIM.vcomponents.all;

entity myip_v1_0 is
generic (
-- Users to add parameters here

-- User parameters ends
-- Do not modify the parameters beyond this line


-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
aclk : in std_logic;
aresetn : in std_logic;
SR0 : in std_logic_vector(31 downto 0);
SR1 : in std_logic_vector(31 downto 0);
sw_rst : out std_logic;
CR0 : out std_logic_vector(31 downto 0);
CR1 : out std_logic_vector(31 downto 0);
-- User ports ends

-- Do not modify the ports beyond this line


-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end myip_v1_0;

architecture arch_imp of myip_v1_0 is

-- component declaration
component myip_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
aclk : in std_logic;
aresetn : in std_logic;
SR0 : in std_logic_vector(31 downto 0);
SR1 : in std_logic_vector(31 downto 0);
sw_rst : out std_logic;
CR0 : out std_logic_vector(31 downto 0);
CR1 : out std_logic_vector(31 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component myip_v1_0_S00_AXI;

COMPONENT DEC_FIFO_32X16
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;

signal fifo_DEC_FIFO_32X16_din : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal fifo_DEC_FIFO_32X16_dout : STD_LOGIC_VECTOR(31 DOWNTO 0);


-- signal aclk : std_logic;
-- signal aresetn : std_logic;
-- signal SR0 : std_logic_vector(31 downto 0);
-- signal SR1 : std_logic_vector(31 downto 0);
-- signal sw_rst : std_logic;
-- signal CR0 : std_logic_vector(31 downto 0);
-- signal CR1 : std_logic_vector(31 downto 0);

signal S0_fifo_full : std_logic;
signal S0_fifo_empty : std_logic;

signal C0_fifo_full : std_logic;
signal C0_fifo_empty : std_logic;

signal S1_fifo_full : std_logic;
signal S1_fifo_empty : std_logic;

signal C1_fifo_full : std_logic;
signal C1_fifo_empty : std_logic;

signal aresetn_d0 : std_logic := '0';
signal aresetn_d1 : std_logic := '0';

signal axi_aresetn_d0 : std_logic := '0';
signal axi_aresetn_d1 : std_logic := '0';

signal sw_rst_d0 : std_logic := '0';
signal sw_rst_d1 : std_logic := '0';


begin

-- Instantiation of Axi Bus Interface S00_AXI
myip_v1_0_S00_AXI_inst : myip_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
aclk => aclk ,
aresetn => aresetn,
SR0 => SR0,
SR1 => SR1,
sw_rst => sw_rst,
CR0 => CR0,
CR1 => CR1,

S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);

-- Add user logic here

CDC_aclk_to_s00_axi_aclk: process (s00_axi_aclk)
begin
if rising_edge(s00_axi_aclk) then
aresetn_d0 <= aresetn;
aresetn_d1 <= aresetn_d0;
end if;
end process CDC_aclk_to_s00_axi_aclk;

CDC_s00_axi_aclk_to_aclk: process (aclk)
begin
if rising_edge(aclk) then
axi_aresetn_d0 <= s00_axi_aresetn;
axi_aresetn_d1 <= axi_aresetn_d0;
--
--sw_rst_d0 <= sw_rst;
--sw_rst_d1 <= sw_rst_d0;
end if;
end process CDC_s00_axi_aclk_to_aclk;

SR0_fifo : DEC_FIFO_32X16
PORT MAP (
rst => '0',
wr_clk => aclk,
rd_clk => s00_axi_aclk,
din => SR0,
wr_en => aresetn,
rd_en => aresetn_d1,
dout => CR0,
full => S0_fifo_full,
empty => S0_fifo_empty
);

SR1_fifo : DEC_FIFO_32X16
PORT MAP (
rst => '0',
wr_clk => aclk,
rd_clk => s00_axi_aclk,
din => SR1,
wr_en => aresetn,
rd_en => aresetn_d1,
dout => CR1,
full => S1_fifo_full,
empty => S1_fifo_empty
);

CR0_fifo : DEC_FIFO_32X16
PORT MAP (
rst => '0',
wr_clk => s00_axi_aclk,
rd_clk => aclk,
din => SR0,
wr_en => s00_axi_aresetn,
rd_en => axi_aresetn_d1,
dout => CR0,
full => C0_fifo_full,
empty => C0_fifo_empty
);


CR1_fifo : DEC_FIFO_32X16
PORT MAP (
rst => '0',
wr_clk => s00_axi_aclk,
rd_clk => aclk,
din => SR1,
wr_en => s00_axi_aresetn,
rd_en => axi_aresetn_d1,
dout => CR1,
full => C1_fifo_full,
empty => C1_fifo_empty
);

--aclk <= aclk;
-- aresetn <= aresetn;


sw_rst <= sw_rst_d1;

end arch_imp;

Buzz McCool

unread,
Mar 18, 2021, 4:15:35 PM3/18/21
to
On 3/18/21 9:45 AM, Ceyhun Sarıkaya wrote:
> Hi
> I am getting this error.
> My block design is this (https://www.linkpicture.com/q/Screenshot-2021-03-18-150349.png)
>
> I think needs to be added Mux in FIFO port map. How could I add MUX inside of this code?

You might have more luck asking on Xilinx's web site.

Have you read this already?
https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Taming-Multiple-Drivers/ba-p/1034745
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